Datasheet > CY7C1510JV18

CY7C1510JV18

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
26页	628K
描述
72-Mbit QDR⑩-II SRAM 2-Word Burst Architecture

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CY7C1510JV18 数据手册

CY7C1510JV18, CY7C1525JV18

CY7C1512JV18, CY7C1514JV18

Pin Definitions (continued)

Pin Name

Pin Description

Echo Clock CQ is Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock

for output data (C) of the QDR-II. In single clock mode, CQ is generated with respect to K. The timing for

the echo clocks is shown in Switching Characteristics on page 22.

Echo Clock CQ is Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock

for output data (C) of the QDR-II. In single clock mode, CQ is generated with respect to K. The timing for

the echo clocks is shown in the Switching Characteristics on page 22.

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

impedance. CQ, CQ, and Q_[x:0]output impedance are set to 0.2 x RQ, where RQ is a resistor connected

between ZQ and ground. Alternatively, connect this pin directly to V_DDQ, which enables the minimum

impedance mode. This pin cannot be connected directly to GND or left unconnected.

DOFF

Input

DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing

in the operation with the DLL turned off differs from those listed in this data sheet. For normal operation,

connect this pin to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR-I mode

when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz

with QDR-I timing.

TDO

Output

Input

N/A

TDO for JTAG.

TCK

TCK Pin for JTAG.

TDI

TDI Pin for JTAG.

TMS

TMS Pin for JTAG.

Not Connected to the Die. Can be tied to any voltage level.

V_SS/144M

V_SS/288M

V_REF

Input

Input-

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC

measurement points.

Reference

V_DD

V_SS

Power Supply Power Supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

V_DDQ

Document #: 001-14435 Rev. *C

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与CY7C1510JV18相关器件

型号	品牌	获取价格	描述	数据表
CY7C1510JV18_09	CYPRESS	获取价格	72-Mbit QDR™-II SRAM 2-Word Burst Architectur
CY7C1510JV18-250BZC	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510JV18-250BZI	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510JV18-250BZXC	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510JV18-250BZXI	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510JV18-267BZC	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510JV18-267BZI	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510JV18-267BZXC	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510JV18-267BZXI	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510KV18	CYPRESS	获取价格	72-Mbit QDR II SRAM 2-Word Burst Architecture Two-word burst on all accesses

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