CY7C1510AV18
CY7C1525AV18
CY7C1512AV18
CY7C1514AV18
PRELIMINARY
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
Input-
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
CY7C1510AV18 - D[7:0]
CY7C1525AV18 - D[8:0]
CY7C1512AV18 - D[17:0]
CY7C1514AV18 - D[35:0]
WPS
Input-
Synchronous
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When
asserted active, a write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D[x:0] to be ignored.
NWS0,NWS1
Nibble Write Select 0,1 − active LOW. (CY7C1510AV18 Only) Sampled on the rising
edge of the K and K clocks during write operations. Used to select which nibble is written
into the device during the current portion of the write operations.Nibbles not written
remain unaltered.NWS0 controls D[3:0] and NWS1 controls D[7:4].All Nibble Write Selects
are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause
the corresponding nibble of data to be ignored and not written into the device.
BWS0, BWS1
BWS2, BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and
K clocks during write operations. Used to select which byte is written into the device
during the current portion of the write operations. Bytes not written remain unaltered.
CY7C1525AV18 − BWS0 controls D[8:0]
,
CY7C1512AV18 − BWS0 controls D[8:0], BWS1 controls D[17:9]
.
CY7C1514AV18 − BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18]
and BWS3 controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte
Write Select will cause the corresponding byte of data to be ignored and not written into
the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K (read address) and K (write
address) clocks during active read and write operations. These address inputs are multi-
plexed for both Read and Write operations. Internally, the device is organized as 8M x 8
(2 arrays each of 4M x 8) for CY7C1510AV18, 8M x 9 (2 arrays each of 4M x 9) for
CY7C1525AV18, 4M x 18 (2 arrays each of 2M x 18) for CY7C1512AV18 and 2M x 36
(2 arrays each of 1M x 36) for CY7C1514AV18. Therefore, only 22 address inputs are
needed to access the entire memory array of CY7C1510AV18 and CY7C1525AV18, 21
address inputs for CY7C1512AV18 and 20 address inputs for CY7C1514AV18. These
inputs are ignored when the appropriate port is deselected.
Q[x:0]
Outputs-
Synchronous
Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Q[x:0] are automatically tri-stated.
CY7C1510AV18 − Q[7:0]
CY7C1525AV18 − Q[8:0]
CY7C1512AV18 − Q[17:0]
CY7C1514AV18 − Q[35:0]
RPS
Input-
Synchronous
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically tri-stated following the next rising edge of the C clock. Each
read access consists of a burst of two sequential transfers.
C
C
Input-Clock
Input-Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the
Read data from the device. C and C can be used together to deskew the flight times of
various devices on the board back to the controller. See application example for further
details.
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the
Read data from the device. C and C can be used together to deskew the flight times of
various devices on the board back to the controller. See application example for further
details.
Document #: 001-06984 Rev. *B
Page 6 of 26
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