CY7C1471V33
CY7C1473V33
CY7C1475V33
PRELIMINARY
Document History Page
Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
with NoBL™ Architecture
Document #: 38-05288
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
114675
121521
08/06/02
02/07/03
PKS
CJM
New Data Sheet
*A
Updated features for package offering
Updated ordering information
Changed Advanced Information to Preliminary
*B
223721
See ECN
NJY
Changed timing diagrams
Changed logic block diagrams
Modified Functional Description
Modified “Functional Overview” section
Added boundary scan order for all packages
Included thermal numbers and capacitance values for all packages
Removed 150-MHz speed grade offering
Included ISB and IDD values
Changed package outline for 165FBGA package and 209-ball BGA package
Removed 119-BGA package offering
*C
*D
*E
235012
243572
299511
See ECN
See ECN
See ECN
RYQ
NJY
SYT
Minor Change: The data sheets do not match on the spec system and
external web.
Changed ball H2 from VDD to NC in the 165-ball FBGA package in page 6
Modified capacitance values on page 21
Removed 117-MHz Speed Bin
Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100
TQFP Package on Page # 21
Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA
Packages
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
*F
320197
331513
See ECN
See ECN
PCI
PCI
Corrected part number typos in the logic block diagram on page# 2
*G
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added Address Expansion pins in the Pin Definitions Table
Added Industrial Operating Range
Modified VOL, VOH Test Conditions
Updated Ordering Information Table
Document #: 38-05288
Page 30 of 30