Datasheet > CY7C1471V25_13

CY7C1471V25_13

更新时间： 2024-09-29 12:52:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
23页	691K
描述
72-Mbit (2 M x 36) Flow-Through SRAM with NoBLâ¢ Architecture

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1471V25_13 数据手册

CY7C1471V25

72-Mbit (2 M × 36) Flow-Through SRAM

with NoBL™ Architecture

72-Mbit (2

M × 36) Flow-Through SRAM with NoBL™ Architecture

Features

Functional Description

■ No Bus Latency™ (NoBL™) architecture eliminates dead

cycles between write and read cycles

The CY7C1471V25 are 2.5 V, 2 M × 36 synchronous flow

through burst SRAMs designed specifically to support unlimited

true back-to-back read or write operations without the insertion

of wait states. The CY7C1471V25 are equipped with the

advanced No Bus Latency (NoBL) logic required to enable

consecutive read or write operations with data transferred on

every clock cycle. This feature dramatically improves the

throughput of data through the SRAM, especially in systems that

require frequent write-read transitions.

■ Supports up to 133 MHz bus operations with zero wait states

■ Data is transferred on every clock

■ Pin compatible and functionally equivalent to ZBT™ devices

■ Internally self timed output buffer control to eliminate the need

to use OE

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock input is qualified by the

clock enable (CEN) signal, which when deasserted suspends

operation and extends the previous clock cycle. Maximum

access delay from the clock rise is 6.5 ns (133-MHz device).

■ Registered inputs for flow through operation

■ Byte write capability

■ 2.5 V I/O supply (V_DDQ

)

■ Fast clock-to-output times

❐ 6.5 ns (for 133-MHz device)

Write operations are controlled by two or four byte write select

(BW_X) and a write enable (WE) input. All writes are conducted

with on-chip synchronous self timed write circuitry.

■ Clock enable (CEN) pin to enable clock and suspend operation

■ Synchronous self timed writes

Three synchronous chip enables (CE₁, CE₂, CE₃) and an

asynchronous output enable (OE) provide easy bank selection

and output tristate control. To avoid bus contention, the output

drivers are synchronously tristated during the data portion of a

write sequence.

■ Asynchronous output enable (OE)

■ CY7C1471V25 available in JEDEC-standard Pb-free 100-pin

TQFP

■ Three chip enables (CE₁, CE₂, CE₃) for simple depth

expansion.

■ Automatic power-down feature available using ZZ mode or CE

deselect.

■ Burst capability – linear or interleaved burst order

■ Low standby power

Selection Guide

Description

Maximum access time

133 MHz Unit

6.5

305

120

Maximum operating current

Maximum CMOS standby current

Errata: For information on silicon errata, see "Errata" on page 19. Details include trigger conditions, devices affected, and proposed workaround.

Cypress Semiconductor Corporation

Document Number: 38-05287 Rev. *P

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 24, 2013

12 3 4 5 6 7...23

中文翻译

下载PDF

与CY7C1471V25_13相关器件

型号	品牌	获取价格	描述	数据表
CY7C1471V25-100AC	CYPRESS	获取价格	ZBT SRAM, 2MX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1471V25-100AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V25-100AXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471V25-100BGC	CYPRESS	获取价格	ZBT SRAM, 2MX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1471V25-100BZC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V25-100BZI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471V25-100BZXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V25-100BZXI	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Throug
CY7C1471V25-117BGC	CYPRESS	获取价格	ZBT SRAM, 2MX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1471V25-133AXC	CYPRESS	获取价格	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture

与CY7C1471V25_13相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

25
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

22
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

22
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

34

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1471V25_13

CY7C1471V25_13 数据手册

与CY7C1471V25_13相关器件

与CY7C1471V25_13相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1471V25_13

CY7C1471V25_13 数据手册

与CY7C1471V25_13相关器件

与CY7C1471V25_13相关文章

您还可以找

您在本页遇到什么问题？