Datasheet > CY7C1461AV33_12

CY7C1461AV33_12

更新时间： 2024-09-28 12:21:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
24页	442K
描述
36-Mbit (1 M Ã 36/2 M Ã 18) Flow-Through SRAM with NoBLâ¢ Architecture

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CY7C1461AV33_12 数据手册

CY7C1461AV33

CY7C1463AV33

36-Mbit (1 M × 36/2 M × 18) Flow-Through

SRAM with NoBL™ Architecture

36-Mbit (1

M × 36/2 M × 18) Flow-Through SRAM with NoBL™ Architecture

Features

Functional Description

■ No Bus Latency™ (NoBL™) architecture eliminates dead

cycles between write and read cycles

The

CY7C1461AV33/CY7C1463AV33

are

3.3 V,

1 M × 36/2 M × 18 Synchronous Flow-Through Burst SRAMs

designed specifically to support unlimited true back-to-back read

and write operations without the insertion of wait states. The

CY7C1461AV33/CY7C1463AV33 is equipped with the advanced

NoBL logic required to enable consecutive read and write

operations with data being transferred on every clock cycle. This

feature dramatically improves the throughput of data through the

SRAM, especially in systems that require frequent write-read

transitions.

■ Supports up to 133 MHz bus operations with zero wait states

❐ Data is transferred on every clock

■ Pin compatible and functionally equivalent to ZBT™ devices

■ Internally self timed output buffer control to eliminate the need

to use OE

■ Registered inputs for flow through operation

■ Byte write capability

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock input is qualified by the

Clock Enable (CEN) signal, which when deasserted suspends

operation and extends the previous clock cycle. Maximum

access delay from the clock rise is 6.5 ns (133 MHz device).

■ 3.3 V and 2.5 V I/O power supply

■ Fast clock-to-output times

❐ 6.5 ns (for 133 MHz device)

Write operations are controlled by the two or four Byte Write

Select (BW_X) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self timed write circuitry.

■ Clock Enable (CEN) pin to enable clock and suspend operation

■ Synchronous self timed writes

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

■ Asynchronous Output Enable

■ CY7C1461AV33,

CY7C1463AV33

available

JEDEC-standard Pb-free 100-pin TQFP package.

■ Three chip enables for simple depth expansion

■ Automatic power down feature available using ZZ mode or CE

deselect

■ Burst capability – linear or interleaved burst order

■ Low standby power

Selection Guide

Description

Maximum Access Time

133 MHz Unit

6.5

310

120

Maximum Operating Current

Maximum CMOS Standby Current

Cypress Semiconductor Corporation

Document Number: 38-05356 Rev. *L

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 24, 2012

12 3 4 5 6 7...24

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与CY7C1461AV33_12相关器件

型号	品牌	获取价格	描述	数据表
CY7C1461AV33-100AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1461AV33-100AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1461AV33-100BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1461AV33-100BZI	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1461AV33-100BZXC	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1461AV33-100BZXI	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1461AV33-133AXC	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1461AV33-133AXCT	CYPRESS	获取价格	ZBT SRAM, 1MX36, 6.5ns, CMOS, PQFP100
CY7C1461AV33-133AXI	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr
CY7C1461AV33-133BZC	CYPRESS	获取价格	36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr

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