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CY7C1461AV33-133AXCT PDF预览

CY7C1461AV33-133AXCT

更新时间： 2024-09-28 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
32页 836K
描述
ZBT SRAM, 1MX36, 6.5ns, CMOS, PQFP100

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CY7C1461AV33-133AXCT 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete包装说明：QFP, QFP100,.63X.87
Reach Compliance Code：compliant风险等级：5.82
Is Samacsys：N最长访问时间：6.5 ns
最大时钟频率 (fCLK)：133 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100内存密度：37748736 bit
内存集成电路类型：ZBT SRAM内存宽度：36
湿度敏感等级：3端子数量：100
字数：1048576 words字数代码：1000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：1MX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK
并行/串行：PARALLEL电源：2.5/3.3,3.3 V
认证状态：Not Qualified最大待机电流：0.12 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.31 mA表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.635 mm
端子位置：QUADBase Number Matches：1

CY7C1461AV33-133AXCT 数据手册

 浏览型号CY7C1461AV33-133AXCT的Datasheet PDF文件第2页浏览型号CY7C1461AV33-133AXCT的Datasheet PDF文件第3页浏览型号CY7C1461AV33-133AXCT的Datasheet PDF文件第4页浏览型号CY7C1461AV33-133AXCT的Datasheet PDF文件第5页浏览型号CY7C1461AV33-133AXCT的Datasheet PDF文件第6页浏览型号CY7C1461AV33-133AXCT的Datasheet PDF文件第7页 
CY7C1461AV33  
CY7C1463AV33, CY7C1465AV33  
36 Mbit (1M x 36/2 M x 18/512K x 72)  
Flow-Through SRAM with NoBL™ Architecture  
Features  
Functional Description  
■ No Bus Latency™ (NoBL™) architecture eliminates dead  
cycles between write and read cycles  
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33[1] are  
3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-Through  
Burst SRAMs designed specifically to support unlimited true  
back-to-back read and write operations without the insertion of  
wait states. The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is  
equipped with the advanced NoBL logic required to enable  
consecutive read and write operations with data being trans-  
ferred on every clock cycle. This feature dramatically improves  
the throughput of data through the SRAM, especially in systems  
that require frequent write-read transitions.  
■ Supports up to 133 MHz bus operations with zero wait states  
❐ Data is transferred on every clock  
■ Pin compatible and functionally equivalent to ZBT™ devices  
■ Internally self timed output buffer control to eliminate the need  
to use OE  
■ Registered inputs for flow through operation  
■ Byte write capability  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. The clock input is qualified by the  
Clock Enable (CEN) signal, which when deasserted suspends  
operation and extends the previous clock cycle. Maximum  
access delay from the clock rise is 6.5 ns (133 MHz device).  
■ 3.3V and 2.5V IO power supply  
■ Fast clock-to-output times  
❐ 6.5 ns (for 133 MHz device)  
Write operations are controlled by the two or four Byte Write  
Select (BWX) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self timed write circuitry.  
■ Clock Enable (CEN) pin to enable clock and suspend operation  
■ Synchronous self timed writes  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. To avoid bus contention,  
the output drivers are synchronously tri-stated during the data  
portion of a write sequence.  
■ Asynchronous Output Enable  
■ CY7C1461AV33, CY7C1463AV33 available in  
JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and  
non Pb-free 165-Ball FBGA package. CY7C1465AV33  
available in Pb-free and non-Pb-free 209-Ball FBGA package  
■ Three chip enables for simple depth expansion  
■ Automatic power down feature available using ZZ mode or CE  
deselect  
■ IEEE 1149.1 JTAG-compatible boundary scan  
■ Burst capability — linear or interleaved burst order  
■ Low standby power  
Selection Guide  
133 MHz  
6.5  
100 MHz  
8.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
310  
290  
mA  
mA  
120  
120  
Note  
1. For best practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05356 Rev. *G  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised May 05, 2008  
[+] Feedback  
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CY7C1461AV33-133AXCT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1461AV33-133AXC CYPRESS

类似代替

 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Thr

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CY7C1461AV33-133BZC CYPRESS

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CY7C1461KV33-133AXC CYPRESS

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 		ZBT SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP
CY7C1461KV33-133AXI CYPRESS

获取价格

 		ZBT SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP
CY7C1461KV33-133AXI INFINEON

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