Datasheet > CY7C1461V25-117BGC

CY7C1461V25-117BGC

更新时间： 2024-11-16 06:19:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
26页	471K
描述
ZBT SRAM, 1MX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1461V25-117BGC 数据手册

浏览型号CY7C1461V25-117BGC的Datasheet PDF文件第2页

浏览型号CY7C1461V25-117BGC的Datasheet PDF文件第3页

浏览型号CY7C1461V25-117BGC的Datasheet PDF文件第4页

浏览型号CY7C1461V25-117BGC的Datasheet PDF文件第5页

浏览型号CY7C1461V25-117BGC的Datasheet PDF文件第6页

CY7C1461V25

CY7C1463V25

CY7C1465V25

PRELIMINARY

1M x 36/2M x 18/512K x 72 F/T SRAM

with NoBL™ Architecture

BWS_c, BWS_d, BWS_e, BWS_f, BWS_g, BWS_h), and read-write

control (WE). BWS_cand BWS_dapply to CY7C1461V25 and

CY7C1465V25 only. BWS_e, BWS_f, BWS_g, and BWS_happly to

CY7C1465V25 only.

Features

• Zero Bus Latency , no dead cycles between write and

read cycles

•Supports 133-MHz bus operations

•1M x 36/2M x18/512K x 72 common I/O

•Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

— 7.5 ns (for 117-MHz device)

Clock Enable (CEN) pin allows operation of the

CY7C1461V25,CY7C1463V25 and CY7C1465V25 to be

suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers

will hold their previous values.

There are three Chip Enable (CE₁, CE₂, CE₃) pins that allow

the user to deselect the device when desired. If any one of

these three are not active when ADV/LD is low, no new

memory operation can be initiated and any burst cycle in

progress is stopped. However, any pending data transfers

(read or write) will be completed. The data bus will be in high

impedance state two cycles after chip is deselected or a write

cycle is initiated.

• Single 2.5V –5% and +5% power supply V_DD

• Separate V_DDQfor 2.5V or 1.8V I/O

• Clock Enable (CEN) pin to suspend operation

• Burst Capability - linear or interleaved burst order

• Available in 119-ball bump BGA, 165-ball FBGA

package and 100-pin TQFP packages (CY7C1461V25

and CY7C1463V25). 209 FBGA package for

CY7C1465V25.

The CY7C1461V25,CY7C1463V25 and CY7C1465V25 have

an on-chip two-bit burst counter. In the burst mode,

CY7C1461V25,CY7C1463V25 and CY7C1465V25 provide

four cycles of data for a single address presented to the

SRAM. The order of the burst sequence is defined by the

MODE input pin. The MODE pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load

a new external address (ADV/LD = LOW) or increment the

internal burst counter (ADV/LD = HIGH)

Functional Description

The CY7C1461V25,CY7C1463V25 and CY7C1465V25

SRAMs are designed to eliminate dead cycles when transi-

tions from Read to Write or vice versa. These SRAMs are

optimized for 100 percent bus utilization and achieves Zero

Bus Latency. They integrate 1,048,576 x 36/2,097,152 x 18/

524,288 x 72 SRAM cells, respectively, with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. The Synchronous Burst SRAM family

employs high-speed, low-power CMOS designs using

advanced single layer polysilicon, three-layer metal

technology. Each memory cell consists of six transistors.

Output Enable (OE) and burst sequence select (MODE) are

the asynchronous signals. OE can be used to disable the

outputs at any given time. ZZ may be tied to LOW if it is not

used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE₁, CE₂, and CE₃), cycle start input (ADV/LD),

Clock Enable (CEN), Byte Write Selects (BWS_a, BWS_b,

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

CEN

CONTROL

and WRITE

LOGIC

1MX36/

2M x18/

512KX72

MEMORY

ARRAY

BWS

X = a, b

, c, d

X = a, b, X= a, b,

X = 19:0

X = 20:0

1Mx36

c, d

Mode

X = a, b

X = a, b X = a, b

2Mx18

X = a, b

X = a, b,

c,d,e,f,g,h

X = a, b,

c,d,e,f,g,h

X = 18:0

512Kx72

c,d,e,f,g,h

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05192 Rev. *B

Revised November 8, 2002

12 3 4 5 6 7...26

中文翻译

下载PDF

与CY7C1461V25-117BGC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1461V25-117BZC	CYPRESS	获取价格	ZBT SRAM, 1MX36, 7.5ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1461V25-133AC	CYPRESS	获取价格	ZBT SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1461V25-133BGC	CYPRESS	获取价格	ZBT SRAM, 1MX36, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1461V25-133BZC	CYPRESS	获取价格	ZBT SRAM, 1MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1461V25-150AC	CYPRESS	获取价格	ZBT SRAM, 1MX36, 5.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1461V33	ETC	获取价格	Memory
CY7C1461V33-117AC	CYPRESS	获取价格	ZBT SRAM, 1MX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1461V33-117BGC	CYPRESS	获取价格	ZBT SRAM, 1MX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1461V33-117BZC	CYPRESS	获取价格	ZBT SRAM, 1MX36, 7.5ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1461V33-133AC	CYPRESS	获取价格	ZBT SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

与CY7C1461V25-117BGC相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

11
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

4
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

30
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

13

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1461V25-117BGC

CY7C1461V25-117BGC 数据手册

与CY7C1461V25-117BGC相关器件

与CY7C1461V25-117BGC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1461V25-117BGC

CY7C1461V25-117BGC 数据手册

与CY7C1461V25-117BGC相关器件

与CY7C1461V25-117BGC相关文章

您还可以找

您在本页遇到什么问题？