Datasheet > 存储 > SRAM> CY7C1411BV18-300BZC

CY7C1411BV18-300BZC

更新时间： 2024-11-27 05:19:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
30页	706K
描述
36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture

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技术参数
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CY7C1411BV18-300BZC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	15 X 17 MM, 1.40 MM HEIGHT, M0-216, FBGA-165
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.88	Is Samacsys：	N
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	300 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	17 mm	内存密度：	33554432 bit
内存集成电路类型：	QDR SRAM	内存宽度：	8
功能数量：	1	端子数量：	165
字数：	4194304 words	字数代码：	4000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	4MX8
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	225
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.37 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.885 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD SILVER
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	15 mm	Base Number Matches：	1

CY7C1411BV18-300BZC 数据手册

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CY7C1411BV18, CY7C1426BV18

CY7C1413BV18, CY7C1415BV18

36-Mbit QDR™-II SRAM 4-Word

Burst Architecture

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

CY7C1411BV18 – 4M x 8

CY7C1426BV18 – 4M x 9

CY7C1413BV18 – 2M x 18

CY7C1415BV18 – 1M x 36

■ 300 MHz clock for high bandwidth

■ 4-word burst for reducing address bus frequency

Functional Description

■ DoubleDataRate(DDR)interfacesonbothreadandwriteports

(data transferred at 600 MHz) at 300 MHz

The CY7C1411BV18, CY7C1426BV18, CY7C1413BV18, and

CY7C1415BV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR™-II architecture. QDR-II architecture

consists of two separate ports to access the memory array. The

read port has dedicated data outputs to support the read opera-

tions and the write port has dedicated data inputs to support the

write operations. QDR-II architecture has separate data inputs

and data outputs to completely eliminate the need to

“turn-around” the data bus required with common IO devices.

Access to each port is through a common address bus.

Addresses for read and write addresses are latched on alternate

rising edges of the input (K) clock. Accesses to the QDR-II read

and write ports are completely independent of one another. To

maximize data throughput, read and write ports are equipped

with DDR interfaces. Each address location is associated with

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR-II operates with 1.5 cycle read latency when DLL is

enabled

four

8-bit

words

(CY7C1411BV18),

9-bit

words

■ Operates as a QDR-I device with 1 cycle read latency in DLL

off mode

(CY7C1426BV18), 18-bit words (CY7C1413BV18), or 36-bit

words (CY7C1415BV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K and C

and C), memory bandwidth is maximized while simplifying

system design by eliminating bus “turn-arounds.”

■ Available in x 8, x 9, x 18, and x 36 configurations

■ Full data coherency, providing most current data

■ Core V_DD= 1.8 (±0.1V); IO V_DDQ= 1.4V to V_DD

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on chip

synchronous self-timed write circuitry.

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Selection Guide

Description

300 MHz

300

278 MHz

278

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

930

865

790

655

570

940

870

795

660

575

x18

x36

1020

1230

950

865

715

615

1140

1040

850

725

Cypress Semiconductor Corporation

Document Number: 001-07037 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 27, 2007

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与CY7C1411BV18-300BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1411BV18-300BZI	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411BV18-300BZXC	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411BV18-300BZXI	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411JV18	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411JV18_09	CYPRESS	获取价格	36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411JV18-200BZC	CYPRESS	获取价格	36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411JV18-200BZI	CYPRESS	获取价格	36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411JV18-200BZXC	CYPRESS	获取价格	36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411JV18-200BZXI	CYPRESS	获取价格	36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411JV18-250BZC	CYPRESS	获取价格	36-Mbit QDR-II SRAM 4-Word Burst Architecture

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