Datasheet > CY7C1411AV18

CY7C1411AV18

更新时间： 2024-11-24 05:19:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		双倍数据速率
页数	文件大小	规格书
8页	244K
描述
RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata

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数据手册

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CY7C1411AV18 数据手册

CY7C129*DV18/CY7C130*DV25

CY7C130*BV18/CY7C130*BV25/CY7C132*BV25

CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18

CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/

CY7C151*V18 /CY7C152*V18

Errata Revision: *C

May 02, 2007

RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata

This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for

QDRI/DDRI/QDRII/DDRII. Details include trigger conditions, possible workarounds and silicon revision applicability.

This document should be used to compare to the respective datasheet for the devices to fully describe the device

functionality.

Please contact your local Cypress Sales Representative for availability of the fixed devices and any other questions.

Devices Affected

Density & Revision

9Mb - Ram9(90 nm)

18Mb - Ram9(90nm)

Part Numbers

CY7C130*DV25

CY7C129*DV18

Architecture

QDRI/DDRI

QDRII

CY7C130*BV18

CY7C130*BV25

CY7C132*BV25

QDRI/DDRI

18Mb - Ram9(90nm)

CY7C131*BV18

CY7C132*BV18

CY7C139*BV18

CY7C191*BV18

QDRII/DDRII

36Mb - Ram9(90nm)

72Mb -Ram9(90nm)

CY7C141*AV18

CY7C142*AV18

QDRII/DDRII

CY7C151*V18

CY7C152*V18

Table 1. List of Affected devices

Product Status

All of the above densities and revisions are available in sample as well as production quantities.

QDR/DDR DOFF Pin, Output Buffer and JTAG Issues Errata Summary

The following table defines the issues and the fix status for the different devices which are affected.

Item

Issue

Device

Fix Status

9Mb - “D” Rev - Ram9 The fix involved removing the in-

18Mb - “B” Rev - Ram9 ternal pull-down resistor on the

36Mb - “A” Rev - Ram9 DOFF pin. The fix has been im-

DOFF pin is used for enabling/dis-

abling the DLL circuitry within the

SRAM. To enable the DLL circuitry,

DOFF pin must be externally tied

HIGH. The QDR-II/DDR-II devices

have an internal pull down resistor of

~5KΩ . The value of the external pull-

72Mb - Ram9

plemented on the new revision

and is now available.

QDR-II/DDR-II Devices

up resistor should be 500Ω or less in

order to ensure DLL is enabled.

Cypress Semiconductor Corporation

Document #: 001-06217 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised:- May 02, 2007

12 3 4 5 6 7 8

中文翻译

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与CY7C1411AV18相关器件

型号	品牌	获取价格	描述	数据表
CY7C1411AV18_09	CYPRESS	获取价格	36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411AV18-167BZC	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-167BZI	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-167BZXC	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-167BZXI	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-200BZC	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-200BZI	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-200BZXC	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-200BZXI	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-250BZC	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur

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