Datasheet > CY7C1411AV18_09

CY7C1411AV18_09

更新时间： 2024-11-27 06:51:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	713K
描述
36-Mbit QDR-II SRAM 4-Word Burst Architecture

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中文翻译

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数据手册

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CY7C1411AV18_09 数据手册

CY7C1411AV18, CY7C1426AV18

CY7C1413AV18, CY7C1415AV18

36-Mbit QDR™-II SRAM 4-Word

Burst Architecture

Features

Functional Description

■ Separate independent read and write data ports

❐ Supports concurrent transactions

The CY7C1411AV18, CY7C1426AV18, CY7C1413AV18, and

CY7C1415AV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR™-II architecture. QDR-II architecture

consists of two separate ports to access the memory array. The

read port has dedicated data outputs to support the read opera-

tions and the write port has dedicated data inputs to support the

write operations. QDR-II architecture has separate data inputs

and data outputs to completely eliminate the need to

“turn-around” the data bus required with common IO devices.

Access to each port is through a common address bus.

Addresses for read and write addresses are latched on alternate

rising edges of the input (K) clock. Accesses to the QDR-II read

and write ports are completely independent of one another. To

maximize data throughput, read and write ports are equipped

with DDR interfaces. Each address location is associated with

■ 300 MHz clock for high bandwidth

■ 4-word burst for reducing address bus frequency

■ DoubleDataRate(DDR)interfacesonbothreadandwriteports

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

four

8-bit

words

(CY7C1411AV18),

9-bit

words

(CY7C1426AV18), 18-bit words (CY7C1413AV18), or 36-bit

words (CY7C1415AV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K and C

and C), memory bandwidth is maximized while simplifying

system design by eliminating bus “turn-arounds.”

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency, providing most current data

■ Core V_DD= 1.8 (±0.1V); IO V_DDQ= 1.4V to V_DD

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on chip

synchronous self-timed write circuitry.

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1411AV18 – 4M x 8

CY7C1426AV18 – 4M x 9

CY7C1413AV18 – 2M x 18

CY7C1415AV18 – 1M x 36

Selection Guide

Description

300 MHz

300

278 MHz

278

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

885

815

745

620

535

900

830

760

620

535

x18

x36

940

865

790

655

565

1040

950

870

715

615

Cypress Semiconductor Corporation

Document Number: 38-05614 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 13, 2008

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与CY7C1411AV18_09相关器件

型号	品牌	获取价格	描述	数据表
CY7C1411AV18-167BZC	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-167BZI	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-167BZXC	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-167BZXI	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-200BZC	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-200BZI	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-200BZXC	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-200BZXI	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-250BZC	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur
CY7C1411AV18-250BZI	CYPRESS	获取价格	36-Mbit QDR⑩-II SRAM 4-Word Burst Architectur

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