Datasheet > 存储 > SRAM> CY7C1386D-250BZI

CY7C1386D-250BZI

更新时间： 2024-02-10 07:12:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
30页	1241K
描述
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C1386D-250BZI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.82	最长访问时间：	2.6 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	250 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	15 mm
内存密度：	18874368 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	36	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512KX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.07 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.35 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	13 mm	Base Number Matches：	1

CY7C1386D-250BZI 数据手册

CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM

Features

Functional Description ^[1]

• Supports bus operation up to 250 MHz

The

CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F

SRAM integrates 512K x 36/1M x 18 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive edge triggered clock

input (CLK). The synchronous inputs include all addresses, all

data inputs, address-pipelining chip enable (CE₁), depth

expansion chip enables (CE₂and CE₃^[2]), burst control inputs

• Available speed grades are 250, 200, and 167 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (double-cycle deselect)

• Depth expansion without wait state

• 3.3V core power supply (V_DD

)

• 2.5V or 3.3V IO power supply (V_DDQ)

• Fast clock-to-output times

(ADSC, ADSP,

ADV), write enables ( , and BWE), and

BW_X

and

global write (GW). Asynchronous inputs include the output

enable (OE) and the ZZ pin.

— 2.6 ns (for 250 MHz device)

Addresses and chip enables are registered at rising edge of

clock when either address strobe processor (ADSP) or

address strobe controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the advance pin (ADV).

• Provides high-performance 3-1-1-1 access rate

• User selectable burst counter supporting Intel^®Pentium^®

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see Pin Configurations on page 3 and Truth Table

^{[4, 5, 6, 7, 8]}on page 9 for further details). Write cycles can be

one to four bytes wide as controlled by the byte write control

inputs. GW active LOW causes all bytes to be written. This

device incorporates an additional pipelined enable register

which delays turning off the output buffers an additional cycle

when a deselect is executed.This feature allows depth

expansion without penalizing system performance.

• Asynchronous output enable

• CY7C1386D/CY7C1387D available in JEDEC-standard

Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball

FBGA package. CY7C1386F/CY7C1387F available in

Pb-free and non Pb-free 119-ball BGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• ZZ sleep mode option

The

CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F

operates from a +3.3V core power supply while all outputs

operate with a +3.3V or +2.5V supply. All inputs and outputs

are JEDEC-standard and JESD8-5-compatible.

Selection Guide

250 MHz

200 MHz

3.0

167 MHz

3.4

Unit

Maximum Access Time

2.6

350

Maximum Operating Current

Maximum CMOS Standby Current

300

275

Notes

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE and CE are for TQFP and 165 FBGA packages only. 119 BGA is offered only in Single Chip Enable.

Cypress Semiconductor Corporation

Document Number: 38-05545 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised Feburary 09, 2007

[+] Feedback

12 3 4 5 6 7...30

下载PDF

与CY7C1386D-250BZI相关器件

型号	品牌	描述	获取价格	数据表
CY7C1386D-250BZXC	CYPRESS	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM	获取价格
CY7C1386D-250BZXI	CYPRESS	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM	获取价格
CY7C1386DV25	CYPRESS	18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM	获取价格
CY7C1386DV25-167AI	CYPRESS	Cache SRAM, 512KX36, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	获取价格
CY7C1386DV25-167AXC	CYPRESS	18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM	获取价格
CY7C1386DV25-167AXI	CYPRESS	18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM	获取价格

与CY7C1386D-250BZI相关文章

PCF8574资料解读：主要参数分析、引脚说明
2024-05-21

7
AD637数据手册解读：主要特性、引脚及其功能解读、电气参数
2024-05-21

6
ADUM1201资料手册解读：参数分析、引脚说明、应用分析
2024-05-21

9
一文带你了解压敏电阻器在直流电路中的过压保护作用
2024-05-21

5

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1386D-250BZI

CY7C1386D-250BZI 技术参数

CY7C1386D-250BZI 数据手册

与CY7C1386D-250BZI相关器件

与CY7C1386D-250BZI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1386D-250BZI

CY7C1386D-250BZI 技术参数

CY7C1386D-250BZI 数据手册

与CY7C1386D-250BZI相关器件

与CY7C1386D-250BZI相关文章

您还可以找

您在本页遇到什么问题？