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CY7C1386DV25-167BZI PDF预览

CY7C1386DV25-167BZI

更新时间： 2024-02-03 21:41:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
30页 1165K
描述
18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM

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CY7C1386DV25-167BZI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA,针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
Is Samacsys：N最长访问时间：3.4 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PBGA-B165
JESD-609代码：e1长度：15 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：165
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX36
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.4 mm
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：20宽度：13 mm
Base Number Matches：1

CY7C1386DV25-167BZI 数据手册

 浏览型号CY7C1386DV25-167BZI的Datasheet PDF文件第2页浏览型号CY7C1386DV25-167BZI的Datasheet PDF文件第3页浏览型号CY7C1386DV25-167BZI的Datasheet PDF文件第4页浏览型号CY7C1386DV25-167BZI的Datasheet PDF文件第5页浏览型号CY7C1386DV25-167BZI的Datasheet PDF文件第6页浏览型号CY7C1386DV25-167BZI的Datasheet PDF文件第7页 
CY7C1386DV25, CY7C1386FV25  
CY7C1387DV25, CY7C1387FV25  
18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM  
Features  
Functional Description [1]  
• Supports bus operation up to 250 MHz  
The  
CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/  
CY7C1387FV25 SRAM integrates 512K x 36 and 1M x 18  
SRAM cells with advanced synchronous peripheral circuitry  
and a two-bit counter for internal burst operation. All  
synchronous inputs are gated by registers controlled by a  
positive edge triggered clock input (CLK). The synchronous  
inputs include all addresses, all data inputs, address-pipelining  
chip enable (CE1), depth expansion chip enables (CE2 and  
CE3 [2]), burst control inputs (ADSC, ADSP, and ADV), write  
enables (BWX, and BWE), and global write (GW).  
Asynchronous inputs include the output enable (OE) and the  
ZZ pin.  
• Available speed grades are 250, 200, and 167 MHz  
• Registered inputs and outputs for pipelined operation  
• Optimal for performance (Double-Cycle deselect)  
• Depth expansion without wait state  
• 2.5V + 5% power supply (VDD  
)
• Fast clock-to-output times, 2.6 ns (for 250 MHz device)  
• Provides high-performance 3-1-1-1 access rate  
• User selectable burst counter supporting Intel® Pentium®  
interleaved or linear burst sequences  
Addresses and chip enables are registered at rising edge of  
clock when either address strobe processor (ADSP) or  
address strobe controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the advance pin (ADV).  
• Separate processor and controller address strobes  
• Synchronous self timed writes  
• Asynchronous output enable  
• CY7C1386DV25/CY7C1387DV25 available in  
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non  
Pb-free 165-ball FBGA package.  
CY7C1386FV25/CY7C1387FV25 available in Pb-free and  
non Pb-free 119-ball BGA package  
Address, data inputs, and write controls are registered on-chip  
to initiate a self timed write cycle.This part supports byte write  
operations (see Pin Definitions on page 6 and Truth Table [4,  
5, 6, 7, 8, 9]  
on page 9 for further details). Write cycles can be  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• ZZ sleep mode option  
one to four bytes wide as controlled by the byte write control  
inputs. GW  
This  
causes all bytes to be written.  
active  
LOW  
device incorporates an additional pipelined enable register  
which delays turning off the output buffers an additional cycle  
when a deselect is executed.This feature allows depth  
expansion without penalizing system performance.  
The  
CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/  
CY7C1387FV25 operates from a +2.5V power supply. All  
inputs  
and  
outputs  
are  
JEDEC-standard  
and  
JESD8-5-compatible.  
Selection Guide  
250 MHz  
200 MHz  
3.0  
167 MHz  
3.4  
Unit  
ns  
Maximum Access Time  
2.6  
350  
70  
Maximum Operating Current  
Maximum CMOS Standby Current  
300  
275  
mA  
mA  
70  
70  
Notes  
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.  
2. CE CE are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.  
3,  
2
Cypress Semiconductor Corporation  
Document Number: 38-05548 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised Feburary 15, 2007  
1234567...30

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CY7C1386DV25-167BZXC CYPRESS 18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM

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CY7C1386DV25-200AXC CYPRESS 18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM

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CY7C1386DV25-200AXI CYPRESS 18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM

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CY7C1386DV25-200BGI CYPRESS Cache SRAM, 512KX36, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119

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CY7C1386DV25-200BGXI CYPRESS Cache SRAM, 512KX36, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119

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