CY7C1386DV25
CY7C1387DV25
18-Mbit (512K x 36/1M x 18)
Pipelined DCD Sync SRAM
Functional Description[1]
Features
• Supports bus operation up to 250 MHz
The CY7C1386DV25/CY7C1387DV25 SRAM integrates
512K x 36 and 1M x 18 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
• Available speed grades are 250, 200 and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
• Depth expansion without wait state
inputs,
address-pipelining
Chip
Enable
(CE1),
• 2.5V + 5% power supply (VDD
)
depth-expansion Chip Enables (CE2 and CE3[2]), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
• Asynchronous output enable
• Available in JEDEC-standard lead-free 100-pin TQFP,
lead-free and non-lead-free 119-Ball BGA and 165-Ball
FBGA packages
controlled by the byte write control inputs. GW
active
LOW
This device incorporates an
causes all bytes to be written.
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
The CY7C1386DV25/CY7C1387DV25 operates from a +2.5V
power supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
250 MHz
2.6
200 MHz
3.0
167 MHz
3.4
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
350
300
275
mA
mA
70
70
70
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE and CE are for TQFP and 165 FBGA package only. 119 BGA is offered only in Single Chip Enable.
3
2
Cypress Semiconductor Corporation
Document #: 38-05548 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 28, 2006
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