Datasheet > 存储 > SRAM> CY7C1372D-250AXI

CY7C1372D-250AXI

更新时间： 2024-11-07 22:21:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
30页	345K
描述
18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture

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技术参数
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CY7C1372D-250AXI 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	LQFP, QFP100,.63X.87	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.3
最长访问时间：	2.6 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	250 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e3
长度：	20 mm	内存密度：	18874368 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	1MX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.07 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.35 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	20	宽度：	14 mm
Base Number Matches：	1

CY7C1372D-250AXI 数据手册

CY7C1370D

CY7C1372D

PRELIMINARY

18-Mbit (512K x 36/1M x 18) Pipelined

SRAM with NoBL™ Architecture

Functional Description

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

The CY7C1370D and CY7C1372D are 3.3V, 512K x 36 and

1 Mbit x 18 Synchronous pipelined burst SRAMs with No Bus

Latency™ (NoBL™) logic, respectively. They are designed to

support unlimited true back-to-back Read/Write operations

with no wait states. The CY7C1370D and CY7C1372D are

equipped with the advanced (NoBL) logic required to enable

consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data in systems that require frequent

Write/Read transitions. The CY7C1370D and CY7C1372D are

pin compatible and functionally equivalent to ZBT devices.

— Available speed grades are 250, 225, 200, and

167 MHz

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

• Single 3.3V power supply

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

• 3.3V/2.5V I/O power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.8 ns (for 225-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.4 ns (for 167-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

Write operations are controlled by the Byte Write Selects

(BW_a–BW_dfor CY7C1370D and BW_a–BW_bfor CY7C1372D)

and a Write Enable (WE) input. All writes are conducted with

on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

• Availableinlead-Free100TQFP,119BGA,and165fBGA

packages

• IEEE 1149.1 JTAG Boundary Scan

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Logic Block Diagram-CY7C1370D (512K x 36)

ADDRESS

A0, A1, A

A1'

A0'

BURST

LOGIC

MODE

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

MEMORY

ARRAY

DQs

DQP

WRITE

DRIVERS

INPUT

READ LOGIC

CE1

CE2

CE3

SLEEP

CONTROL

Cypress Semiconductor Corporation

Document #: 38-05555 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised October 12, 2004

12 3 4 5 6 7...30

中文翻译

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CY7C1372D-250AXI 替代型号

型号	品牌	替代类型	描述	数据表
MT55L1MY18PT-6	CYPRESS	功能相似	ZBT SRAM, 1MX18, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
CY7C1372B-167AC	CYPRESS	功能相似	512K 】 36/1M 】 18 Pipelined SRAM with NoBL Ar
CY7C1372D-250AXC	CYPRESS	功能相似	18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture

与CY7C1372D-250AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1372D-250BGC	CYPRESS	获取价格	18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-250BGI	CYPRESS	获取价格	18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-250BGXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL? Architecture
CY7C1372D-250BGXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL? Architecture
CY7C1372D-250BZC	CYPRESS	获取价格	18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-250BZI	CYPRESS	获取价格	18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-250BZXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL? Architecture
CY7C1372D-250BZXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL? Architecture
CY7C1372DV25	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM wi
CY7C1372DV25-167	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM wi

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