CY7C1370B-167BGC

更新时间： 2024-11-16 05:09:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
27页	759K
描述
512K 】 36/1M 】 18 Pipelined SRAM with NoBL Architecture

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技术参数
数据手册

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CY7C1370B-167BGC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	14 X 22 MM, 2.40 MM HEIGHT, BGA-119
针数：	119	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.78	Is Samacsys：	N
最长访问时间：	3.4 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	167 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B119	JESD-609代码：	e0
长度：	22 mm	内存密度：	18874368 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	36
功能数量：	1	端子数量：	119
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	512KX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA119,7X17,50
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
座面最大高度：	2.4 mm	最大待机电流：	0.02 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.285 mA	最大供电电压 (Vsup)：	3.63 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

CY7C1370B-167BGC 数据手册

CY7C1370B

CY7C1372B

512K × 36/1M × 18 Pipelined SRAM with NoBL Architecture

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE₁, CE₂, and CE₃), cycle start input (ADV/LD),

Features

• Zero Bus Latency, no dead cycles between Write and

Clock enable (CEN), byte Write Enables (BWSa, BWSb,

BWSc, and BWSd), and Read-Write Control (WE). BWSc and

BWSd apply to CY7C1370B only.

Read cycles

• Fast clock speed: 200, 167, 150, and 133 MHz

• Fast access time: 3.0, 3.4, 3.8, and 4.2 ns

• Internally synchronized registered outputs eliminate

the need to control OE

Address and control signals are applied to the SRAM during

one clock cycle, and two cycles later, its associated data

occurs, either Read or Write.

• Single 3.3V –5% and +10% power supply V_DD

• Separate V_DDQfor 3.3V or 2.5V I/O

• Single WE (Read/Write) control pin

• Positive clock-edge triggered address, data, and

control signal registers for fully pipelined applications

Clock enable (CEN) pin allows operation of the

CY7C1370B/CY7C1372B to be suspended as long as

necessary. All synchronous inputs are ignored when CEN is

HIGH and the internal device registers will hold their previous

values.

There are three chip enable pins (CE₁, CE₂, CE₃) that allow

the user to deselect the device when desired. If any one of

these three are not active when ADV/LD is LOW, no new

memory operation can be initiated and any burst cycle in

progress is stopped. However, any pending data transfers

(Read or Write) will be completed. The data bus will be in

high-impedance state two cycles after the chip is deselected

or a Write cycle is initiated.

• Interleaved or linear four-word burst capability

• Individual byte Write (BWSa–BWSd) control (may be

tied LOW)

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• JTAG boundary scan (BGA package only)

• Available in 119-ball bump BGA and 100-pin TQFP

packages

The CY7C1370B and CY7C1372B have an on-chip two-bit

burst counter. In the burst mode, the CY7C1370B and

CY7C1372B provide four cycles of data for a single address

presented to the SRAM. The order of the burst sequence is

defined by the MODE input pin. The MODE pin selects

between linear and interleaved burst sequence. The ADV/LD

signal is used to load a new external address (ADV/LD = LOW)

or increment the internal burst counter (ADV/LD = HIGH)

• Automatic power down available using ZZ mode or CE

deselect

Functional Description

The CY7C1370B and CY7C1372B SRAMs are designed to

eliminate dead cycles when transitions from Read to Write or

vice versa. These SRAMs are optimized for 100 percent bus

utilization and achieve Zero Bus Latency. They integrate

524,288 × 36 and 1,048,576 × 18 SRAM cells, respectively,

with advanced synchronous peripheral circuitry and a 2-bit

counter for internal burst operation. The Synchronous Burst

SRAM family employs high-speed, low-power CMOS designs

using advanced single-layer polysilicon, three-layer metal

technology. Each memory cell consists of six transistors.

Output enable (OE) and burst sequence select (MODE) are

the asynchronous signals. OE can be used to disable the

outputs at any given time. ZZ may be tied to LOW if it is not

used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock input (CLK). The synchronous

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

CEN

CONTROL

and Write

LOGIC

256K × 36/

512K × 18

MEMORY

ARRAY

BWS

CY7C1370 CY7C1372

X = 18:0 X = 19:0

Mode

X = a, b, c, d X = a, b

BWS

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05197 Rev. **

Revised December 3, 2001

12 3 4 5 6 7...27

中文翻译

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与CY7C1370B-167BGC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1370B-167BGI	CYPRESS	获取价格	512K 】 36/1M 】 18 Pipelined SRAM with NoBL Ar
CY7C1370B-167BZC	CYPRESS	获取价格	512K 】 36/1M 】 18 Pipelined SRAM with NoBL Ar
CY7C1370B-167BZI	CYPRESS	获取价格	512K 】 36/1M 】 18 Pipelined SRAM with NoBL Ar
CY7C1370B-200AC	CYPRESS	获取价格	512K 】 36/1M 】 18 Pipelined SRAM with NoBL Ar
CY7C1370B-200BGC	CYPRESS	获取价格	512K 】 36/1M 】 18 Pipelined SRAM with NoBL Ar
CY7C1370B-200BZC	CYPRESS	获取价格	512K 】 36/1M 】 18 Pipelined SRAM with NoBL Ar
CY7C1370BV25	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1370BV25-133AC	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1370BV25-133AI	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1370BV25-133BGC	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture

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