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CY7C136-25JXC PDF预览

CY7C136-25JXC

更新时间： 2024-09-28 05:09:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 内存集成电路静态存储器
页数 文件大小 规格书
18页 564K
描述
2K x 8 Dual-Port Static RAM

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中文翻译

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CY7C136-25JXC 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：LCC包装说明：ROHS COMPLIANT, PLASTIC, LCC-52
针数：52Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：8.48最长访问时间：25 ns
I/O 类型：COMMONJESD-30 代码：S-PQCC-J52
JESD-609代码：e3长度：19.1262 mm
内存密度：16384 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：8湿度敏感等级：3
功能数量：1端口数量：2
端子数量：52字数：2048 words
字数代码：2000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2KX8输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC52,.8SQ封装形状：SQUARE
封装形式：CHIP CARRIER并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：5 V
认证状态：Not Qualified座面最大高度：5.08 mm
最大待机电流：0.015 A最小待机电流：4.5 V
子类别：SRAMs最大压摆率：0.17 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：19.1262 mm
Base Number Matches：1

CY7C136-25JXC 数据手册

 浏览型号CY7C136-25JXC的Datasheet PDF文件第2页浏览型号CY7C136-25JXC的Datasheet PDF文件第3页浏览型号CY7C136-25JXC的Datasheet PDF文件第4页浏览型号CY7C136-25JXC的Datasheet PDF文件第5页浏览型号CY7C136-25JXC的Datasheet PDF文件第6页浏览型号CY7C136-25JXC的Datasheet PDF文件第7页 
CY7C132/CY7C136  
CY7C142/CY7C146  
2K x 8 Dual-Port Static RAM  
Features  
Functional Description  
• True Dual-Ported memory cells which allow simulta-  
neous reads of the same memory location  
The CY7C132/CY7C136/CY7C142 and CY7C146 are  
high-speed CMOS 2K by 8 dual-port static RAMs. Two ports  
are provided to permit independent access to any location in  
memory. The CY7C132/ CY7C136 can be utilized as either a  
standalone 8-bit dual-port static RAM or as a MASTER  
dual-port RAM in conjunction with the CY7C142/CY7C146  
SLAVE dual-port device in systems requiring 16-bit or greater  
word widths. It is the solution to applications requiring shared  
or buffered data such as cache memory for DSP, bit-slice, or  
multiprocessor designs.  
• 2K x 8 organization  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 15 ns  
• Low operating power: ICC = 110 mA (max.)  
• Fully asynchronous operation  
• Automatic power-down  
Each port has independent control pins; chip enable (CE),  
write enable (R/W), and output enable (OE). BUSY flags are  
provided on each port. In addition, an interrupt flag (INT) is  
provided on each port of the 52-pin PLCC version. BUSY  
signals that the port is trying to access the same location  
currently being accessed by the other port. On the PLCC  
version, INT is an interrupt flag indicating that data has been  
placed in a unique location (7FF for the left port and 7FE for  
the right port).  
• Master CY7C132/CY7C136 easily expands data bus  
width to 16 or more bits using slave CY7C142/CY7C146  
• BUSY output flag on CY7C132/CY7C136; BUSY input  
on CY7C142/CY7C146  
• INT flag for port-to-port communication (52-pin  
PLCC/PQFP versions)  
• Availablein48-pinDIP(CY7C132/142),52-pinPLCCand  
52-pin TQFP (CY7C136/146)  
An automatic power-down feature is controlled independently  
on each port by the chip enable (CE) pins.  
• Pb-Free packages available  
The CY7C132/CY7C142 are available in 48-pin DIP. The  
CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.  
Logic Block Diagram  
Pin Configuration  
R/W  
L
R/W  
R
DIP  
CE  
L
CE  
R
Top View  
OE  
L
OE  
R
V
48  
1
CE  
L
CC  
CE  
R/W  
R
R/W  
BUSY  
47  
L
R
2
46  
3
L
BUSY  
45  
A
10L  
R
4
A
44  
5
I/O  
I/O  
OE  
10R  
OE  
I/O  
I/O  
7L  
L
7R  
I/O  
CONTROL  
I/O  
CONTROL  
A
0L  
43  
R
6
42  
7
A
0R  
0R  
A
1L  
A
2L  
A
3L  
0L  
[1]  
A
1R  
A
2R  
41  
[1]  
8
BUSY  
BUSY  
R
L
40  
9
A
A
A
39  
10  
3R  
4L  
5L  
A
A
A
10L  
10R  
0R  
MEMORY  
ARRAY  
A
4R  
A
5R  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
38  
37  
11  
12  
A
6L  
A
7L  
A
8L  
7C132  
A
0L  
A
6R  
13 7C142  
36  
35  
34  
A
7R  
A
8R  
14  
15  
16  
17  
18  
A
9L  
I/O  
0L  
I/O  
1L  
A
9R  
33  
32  
I/O  
ARBITRATION  
LOGIC  
(7C132/7C136 ONLY)  
AND  
INTERRUPTLOGIC  
(7C136/7C146 ONLY)  
7R  
I/O  
2L  
I/O  
3L  
I/O  
I/O  
I/O  
I/O  
I/O  
31  
30  
29  
28  
27  
26  
25  
6R  
5R  
4R  
3R  
2R  
19  
20  
21  
22  
23  
24  
CE  
L
I/O  
4L  
I/O  
5L  
CE  
R
OE  
L
OE  
R
I/O  
I/O  
6L  
R/W  
L
R/W  
R
I/O  
I/O  
1R  
7L  
GND  
0R  
[2]  
[2]  
INT  
INT  
R
L
Notes:  
1. CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor.  
CY7C142/CY7C146 (Slave): BUSY is input.  
2. Open drain outputs; pull-up resistor required.  
Cypress Semiconductor Corporation  
Document #: 38-06031 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 1, 2005  
1234567...18

中文翻译

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CY7C136-25JXC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C136E-25NXC CYPRESS

完全替代

 1 K / 2 K × 8 Dual-port Static RAM
CY7C136E-25JXC CYPRESS

完全替代

 1 K / 2 K × 8 Dual-port Static RAM
CY7C136-25JC CYPRESS

完全替代

 2Kx8 Dual-Port Static RAM

与CY7C136-25JXC相关器件

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CY7C136-25JXCT CYPRESS

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 		Multi-Port SRAM, 2KX8, 25ns, CMOS, PQCC52, ROHS COMPLIANT, PLASTIC, LCC-52
CY7C136-25JXI CYPRESS

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 		2K x 8 Dual-Port Static RAM
CY7C136-25LC CYPRESS

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 		Multi-Port SRAM, 2KX8, 25ns, CMOS, CQCC52, CERAMIC, LCC-52
CY7C136-25NC CYPRESS

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 		2Kx8 Dual-Port Static RAM
CY7C136-25NXC CYPRESS

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 		2K x 8 Dual-Port Static RAM
CY7C1362A CYPRESS

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 		256K x 36/512K x 18 Synchronous Pipelined Burst SRAM
CY7C1362A1-150AJC CYPRESS

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 		Standard SRAM, 512KX18, 4.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10
CY7C1362A1-150BGC CYPRESS

获取价格

 		Standard SRAM, 512KX18, 4.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CY7C1362A1-166AC CYPRESS

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 		Standard SRAM, 512KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1362A1-166BGC CYPRESS

获取价格

 		Standard SRAM, 512KX18, 4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119

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