Datasheet > CY7C136E-25NXC

CY7C136E-25NXC

更新时间： 2024-11-27 12:21:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
19页	347K
描述
1 K / 2 K Ã 8 Dual-port Static RAM

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CY7C136E-25NXC 数据手册

CY7C131E, CY7C131AE

CY7C136E, CY7C136AE

1 K / 2 K × 8 Dual-port Static RAM

K / 2 K × 8 Dual-port Static RAM

Features

Functional Description

■ True dual-ported memory cells, which allow simultaneous

reads of the same memory location

CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are

high-speed, low-power CMOS 1 K / 2 K × 8 dual-port static

RAMs. Two ports are provided permitting independent access to

any location in memory. The CY7C131E / CY7C131AE /

CY7C136E / CY7C136AE can be used as a standalone dual-port

static RAM. It is the solution to applications requiring shared or

buffered data, such as cache memory for DSP, bit-slice, or multi-

processor designs.

■ 1 K / 2 K × 8 organization

■ 0.35 micron complementary metal oxide semiconductor

(CMOS) for optimum speed and power

■ High speed access: 15 ns

■ Low operating power: I_CC= 110 mA (typical),

Each port has independent control pins; chip enable (CE), write

enable (R/W), and output enable (OE). Two flags are provided

on each port, BUSY and INT. The BUSY flag signals that the port

is trying to access the same location, which is currently being

accessed by the other port. The INT is an interrupt flag indicating

that data is placed in a unique location^[1]. The BUSY and INT

flags are push pull outputs. An automatic power-down feature is

controlled independently on each port by the chip enable (CE)

pins.

Standby: I_SB3= 0.05 mA (typical)

■ Fully asynchronous operation

■ Automatic power-down

■ BUSY output flag to indicate access to the same location by

both ports

■ INT flag for port-to-port communication

■ Available in 52-pin plastic leaded chip carrier (PLCC), 52-pin

plastic quad flat package (PQFP)

The CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are

available in 52-pin Pb-free PLCC and 52-pin Pb-free PQFP.

■ Pb-free packages available

Logic Block Diagram

I/O

CONTROL

I/O

CONTROL

[2]

[4]

BUSY

9/10L

9/10R

MEMORY

ARRAY

ADDR

DECODER

ADDR

DECODER

[4]

7C131E/7C131AE/

ARBITRATION

7C136E/7C136AE

LOGIC

ARBITRATION LOGIC

(7C130/7C131 ONLY)

AND

INTERRUPT LOGIC

R/W

[3]

INT

Notes

1. Unique location used by interrupt flag: 1 K × 8: Left port reads from 3FE, Right port reads from 3FF; 2 K × 8: Left port reads from 7FE, Right port reads from 7FF.

2. BUSY is a push-pull output. No pull-up resistor required.

3. INT: push-pull output. No pull-up resistor required.

4. 1 K × 8: A0–A9, 2 K × 8: A0–A10, address lines are for both left and right ports.

Cypress Semiconductor Corporation

Document Number: 001-64231 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 15, 2012

12 3 4 5 6 7...19

中文翻译

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CY7C136E-25NXC 替代型号

型号	品牌	替代类型	描述	数据表
CY7C136-25JXC	CYPRESS	完全替代	2K x 8 Dual-Port Static RAM
CY7C136-25JC	CYPRESS	完全替代	2Kx8 Dual-Port Static RAM
CY7C146-25JC	CYPRESS	完全替代	2Kx8 Dual-Port Static RAM

与CY7C136E-25NXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C136E-55JXC	CYPRESS	获取价格	1 K / 2 K Ã 8 Dual-port Static RAM
CY7C136E-55NXC	CYPRESS	获取价格	1 K / 2 K Ã 8 Dual-port Static RAM
CY7C1370AV25-150AC	CYPRESS	获取价格	ZBT SRAM, 512KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1370B	CYPRESS	获取价格	512K 】 36/1M 】 18 Pipelined SRAM with NoBL Ar
CY7C1370B-133AC	CYPRESS	获取价格	512K 】 36/1M 】 18 Pipelined SRAM with NoBL Ar
CY7C1370B-133AI	CYPRESS	获取价格	512K 】 36/1M 】 18 Pipelined SRAM with NoBL Ar
CY7C1370B-133BGC	CYPRESS	获取价格	512K 】 36/1M 】 18 Pipelined SRAM with NoBL Ar
CY7C1370B-133BGI	CYPRESS	获取价格	512K 】 36/1M 】 18 Pipelined SRAM with NoBL Ar
CY7C1370B-133BZC	CYPRESS	获取价格	512K 】 36/1M 】 18 Pipelined SRAM with NoBL Ar
CY7C1370B-133BZI	CYPRESS	获取价格	512K 】 36/1M 】 18 Pipelined SRAM with NoBL Ar

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