CY7C1325A/GVT71256E18
Pin Configurations (continued)
119-Ball Bump BGA
256Kx18—CY7C1325A/GVT71256E18
Top View
1
2
3
A4
4
ADSP
ADSC
VCC
NC
5
6
A16
CE2
A15
DQ”P1
NC
7
A
B
C
D
E
F
VCCQ
A6
A8
VCCQ
NC
NC
NC
CE2
A7
A3
A9
A2
A12
VSS
VSS
VSS
VSS
VSS
NC
NC
DQ9
NC
NC
VSS
VSS
VSS
BWH
VSS
NC
NC
DQ10
NC
CE
DQ8
VCCQ
DQ6
NC
VCCQ
NC
OE
DQ7
NC
G
H
J
DQ11
NC
ADV
GW
VCC
CLK
NC
DQ12
VCCQ
NC
DQ5
VCC
NC
VCC
DQ13
NC
VCCQ
DQ4
NC
K
L
VSS
VSS
VSS
VSS
VSS
MODE
A11
NC
VSS
BWL
VSS
VSS
VSS
NC
DQ14
VCCQ
DQ18
NC
DQ3
NC
M
N
P
R
T
DQ15
NC
BWE
A1
VCCQ
NC
DQ2
NC
DQP2
A5
A0
DQ1
NC
NC
VCC
NC
A13
A17
NC
NC
A10
NC
A14
NC
ZZ
U
VCCQ
NC
VCCQ
Pin Descriptions
Pin
Name
BGA Pins
QFP Pins
Type
Input-
Description
Addresses: These inputs are registered and must meet the set-up
4P, 4N, 2A, 3A, 37, 36, 35, 34, A0–A17
5A, 6A, 3B, 5B, 33, 32, 100, 99,
2C, 3C, 5C, 6C, 82, 81, 80, 48,
2R, 6R, 2T, 3T, 47, 46, 45, 44,
Synchronous and hold times around the rising edge of CLK. The burst counter
generates internal addresses associated with A0 and A1, during
burst cycle and wait cycle.
5T, 6T
49, 50
5L, 3G
93, 94
WEL,
Input-
Byte Write Enables: A byte write enable is LOW for a Write cycle
WEH Synchronous and HIGH for a Read cycle. WEL controls DQ1–DQ8 and DQP1.
WEH controls DQ9–DQ16 and DQP2. Data I/O are high-imped-
ance if either of these inputs are LOW, conditioned by BWE being
LOW.
4M
4H
4K
87
88
89
BWE
Input-
Write Enable: This active LOW input gates byte write operations
Synchronous and must meet the set-up and hold times around the rising edge of
CLK.
GW
Input-
Global Write: This active LOW input allows a full 18-bit Write to
Synchronous occur independent of the BWE and WEn lines and must meet the
set-up and hold times around the rising edge of CLK.
CLK
Input-
Clock: This signal registers theaddresses, data, chip enables, write
Synchronous control and burst control inputs on its rising edge. All synchronous
inputs must meet set-up and hold times around the clock’s rising
edge.
Document #: 38-05118 Rev. *A
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