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CY7C128-20VC PDF预览

CY7C128-20VC

更新时间： 2024-01-17 04:19:22
品牌 Logo 应用领域
其他 - ETC 静态存储器
页数 文件大小 规格书
9页 281K
描述
IC-16K CMOS SRAM

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中文翻译

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CY7C128-20VC 数据手册

 浏览型号CY7C128-20VC的Datasheet PDF文件第2页浏览型号CY7C128-20VC的Datasheet PDF文件第3页浏览型号CY7C128-20VC的Datasheet PDF文件第4页浏览型号CY7C128-20VC的Datasheet PDF文件第5页浏览型号CY7C128-20VC的Datasheet PDF文件第6页浏览型号CY7C128-20VC的Datasheet PDF文件第7页 
CY7C128A  
2K x 8 Static RAM  
provided by an active LOW Chip Enable (CE), and active LOW  
Output Enable (OE) and three-state drivers. The CY7C128A  
has an automatic power-down feature, reducing the power  
consumption by 83% when deselected.  
Features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• High speed  
Writing to the device is accomplished when the Chip Enable  
(CE) and Write Enable (WE) inputs are both LOW.  
— 15 ns  
Data on the eight I/O pins (I/O through I/O ) is written into the  
• Low active power  
0
7
memory location specified on the address pins (A through  
0
— 660 mW (commercial)  
— 688 mW (military—20 ns)  
• Low standby power  
A
).  
10  
Reading the device is accomplished by taking Chip Enable  
(CE) and Output Enable (OE) LOW while Write Enable (WE)  
remains HIGH. Under these conditions, the contents of the  
memory location specified on the address pins will appear on  
the eight I/O pins.  
— 110 mW (20 ns)  
• TTL-compatible inputs and outputs  
• Capable ofwithstanding greaterthan 2001V electrostat-  
ic discharge  
The I/O pins remain in high-impedance state when Chip En-  
able (CE) or Output Enable (OE) is HIGH or Write Enable (WE)  
is LOW.  
• V of 2.2V  
IH  
Functional Description  
The CY7C128A utilizes a die coat to insure alpha immunity.  
The CY7C128A is a high-performance CMOS static RAM or-  
ganized as 2048 words by 8 bits. Easy memory expansion is  
Pin  
Logic Block Diagram  
Configurations  
DIP/SOJ/SOIC  
Top View  
A
V
CC  
1
24  
23  
22  
7
A
A
A
A
8
A
9
2
3
4
5
6
7
8
9
6
5
4
WE  
OE  
21  
20  
19  
18  
17  
A
A
A
3
2
1
0
0
A
10  
7C128A  
CE  
I/O  
A
7
I/O  
I/O  
6
0
I/O  
16  
15  
14  
13  
INPUT BUFFER  
I/O  
I/O  
10  
11  
12  
I/O  
I/O  
GND  
5
1
2
4
I/O  
1
A
10  
I/O  
3
A
9
I/O  
2
C128A–2  
A
LCC  
8
Top View  
A
7
I/O  
3
128 x 16 x 8  
ARRAY  
A
6
I/O  
4
A
5
3 2 1 2423  
4
5
6
7
8
9
22  
A
A
4
9
A
4
I/O  
21  
20  
19  
18  
17  
16  
A
WE  
OE  
10  
CE  
5
3
2
A
A
A
1
7C128A  
CE  
WE  
I/O  
A
6
0
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
0
I/O  
7
10  
I/O  
1
I/O  
6
I/O  
11 12 13 14 15  
7
OE  
C128A–3  
C128A–1  
A
3
A
2
A
1
A
0
Selection Guide  
7C128A-15  
7C128A-20  
7C128A-25  
7C128A-35  
7C128A-45  
Maximum Access Time (ns)  
15  
120  
-
20  
120  
125  
20  
25  
120  
125  
20  
35  
120  
125  
20  
45  
120  
125  
20  
Maximum Operating  
Current (mA)  
Commercial  
Military  
Maximum Standby  
Current (mA)  
Commercial  
Military  
40  
-
20  
20  
20  
20  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
February 3, 2000  
1234567...9

中文翻译

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