Datasheet > CY7C128A_06

CY7C128A_06

更新时间： 2024-09-25 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	255K
描述
2K x 8 Static RAM

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中文翻译

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数据手册

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CY7C128A_06 数据手册

CY7C128A

2K x 8 Static RAM

Features

Functional Description

• Automatic power-down when deselected

• CMOS for optimum speed/power

• High speed

The CY7C128A is a high-performance CMOS static RAM

organized as 2048 words by 8 bits. Easy memory expansion

is provided by an active LOW Chip Enable (CE), and active

LOW Output Enable (OE) and tri-state drivers. The CY7C128A

has an automatic power-down feature, reducing the power

consumption by 83% when deselected.

— 15 ns

• Low active power

Writing to the device is accomplished when the Chip Enable

(CE) and Write Enable (WE) inputs are both LOW.

— 660 mW (commercial)

• Low standby power

Data on the eight I/O pins (I/O₀through I/O₇) is written into the

memory location specified on the address pins (A₀through

— 110 mW (20 ns)

A₁₀).

• TTL-compatible inputs and outputs

Reading the device is accomplished by taking Chip Enable

(CE) and Output Enable (OE) LOW while Write Enable (WE)

remains HIGH. Under these conditions, the contents of the

memory location specified on the address pins will appear on

the eight I/O pins.

• Capable of withstanding greater than 2001V electro-

static discharge

• Available in Pb-free and non Pb-free 24-pin Molded

SOJ, non Pb-free 24-pin (300-Mil) Molded DIP

The I/O pins remain in high-impedance state when Chip

Enable (CE) or Output Enable (OE) is HIGH or Write Enable

(WE) is LOW.

The CY7C128A utilizes a die coat to insure alpha immunity.

Logic Block Diagram

Configurations

DIP/SOJ

Top View

I/O

INPUT BUFFER

7C128A

I/O

128 x 16 x 8

ARRAY

GND

I/O

C128A–2

POWER

DOWN

COLUMN

DECODER

I/O

C128A–1

Cypress Semiconductor Corporation

Document #: 38-05028 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 3, 2006

12 3 4 5 6 7...9

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