Datasheet > CY7C1157V18-300BZXC

CY7C1157V18-300BZXC

更新时间： 2024-01-06 05:43:33

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
27页	645K
描述
DDR SRAM, 2MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165

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CY7C1157V18-300BZXC 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA, BGA165,11X15,40	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.84
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	300 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	15 mm	内存密度：	18874368 bit
内存集成电路类型：	DDR SRAM	内存宽度：	9
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2MX9	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	0.25 A	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.85 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	宽度：	13 mm
Base Number Matches：	1

CY7C1157V18-300BZXC 数据手册

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CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

Pin Definitions

Pin Name

Pin Description

DQ_[x:0]

Input Output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks when write

Synchronous operations are valid. These pins drive out the requested data when a read operation is active. Valid

data is driven out on the rising edge of both the K and K clocks when read operations are active.

When read access is deselected, Q_[x:0]are automatically tri-stated.

CY7C1146V18 − DQ_[7:0]

CY7C1157V18 − DQ_[8:0]

CY7C1148V18 − DQ_[17:0]

CY7C1150V18 − DQ_[35:0]

Input-

Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined. This

Synchronous definition includes address and read/write direction. All transactions operate on a burst of two data.

LD must meet the setup and hold times around edge of K.

Input-

Synchronous and K clocks when the write operation is active. It is used to select the nibble that is written into the

device NWS₀controls D_[3:0]and NWS₁controls D_[7:4]

Nibble Write Select 0, 1 − Active LOW.(CY7C1146V18 Only) Sampled on the rising edge of the K

NWS₀, NWS₁

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write

Select causes the corresponding nibble of data to be ignored and not written into the device.

BWS₀, BWS₁,

Input-

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks

BWS₂, BWS₃Synchronous when the Write operation is active. It is used to select the byte that is written into the device when

the current portion of the write operation is active. Bytes not written remain unaltered.

CY7C1157V18 − BWS₀controls D_[8:0]

CY7C1148V18 − BWS₀controls D_[8:0], and BWS₁controls D_[17:9].

CY7C1148V18 − BWS₀controls D_[8:0], BWS₁controls D_[17:9], BWS₂controls D_[26:18], and BWS₃

controls D_[35:27]

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

causes the corresponding byte of data to be ignored and not written into the device.

Input-

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.

Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is

organized as 2M x 8 (two arrays each of1M x 8) for CY7C1146V18, 2M x 9 (two arrays each of 1M

x 9) for CY7C1157V18, 1M x 18 (two arrays each of 512K x 18) for CY7C1148V18, and 512K x 36

(two arrays each of 256K x 18) for CY7C1150V18. All the address inputs are ignored when the

appropriate port is deselected.

R/W

Input-

Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read

Synchronous when R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold

times around edge of K.

QVLD

Valid Output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and

Indicator

CQ.

Input-

Clock

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

and to drive out data through Q_[x:0]when in single clock mode. All accesses are initiated on the rising

edge of K.

Input-

Clock

Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device

and to drive out data through Q_[x:0]when in single clock mode.

Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input

clock (K) of the DDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”

on page 22.

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input

clock (K) of the DDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”

on page 22.

Clock Output

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data

bus impedance. CQ, CQ, and Q_[x:0]output impedance are set to 0.2 x RQ, where RQ is a resistor

connected between ZQ and ground. Alternatively, connect this pin directly to V_DDQ, which enables

the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

Document Number: 001-06621 Rev. *D

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与CY7C1157V18-300BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1157V18-300BZXI	CYPRESS	获取价格	DDR SRAM, 2MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA
CY7C1157V18-333BZC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1157V18-333BZI	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1157V18-333BZXC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1157V18-333BZXI	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1157V18-375BZC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1157V18-375BZI	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1157V18-375BZXC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1157V18-375BZXI	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C11611KV18	CYPRESS	获取价格	18-Mbit QDR? II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

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