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CY7C1021-12

更新时间： 2024-11-08 22:33:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 184K
描述
64K x 16 Static RAM

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中文翻译

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CY7C1021-12 数据手册

 浏览型号CY7C1021-12的Datasheet PDF文件第2页浏览型号CY7C1021-12的Datasheet PDF文件第3页浏览型号CY7C1021-12的Datasheet PDF文件第4页浏览型号CY7C1021-12的Datasheet PDF文件第5页浏览型号CY7C1021-12的Datasheet PDF文件第6页浏览型号CY7C1021-12的Datasheet PDF文件第7页 
021  
CY7C1021  
64K x 16 Static RAM  
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O9 through I/O16) is written into the location  
specified on the address pins (A0 through A15).  
Features  
• High speed  
— tAA = 12 ns  
• CMOS for optimum speed/power  
• Low active power  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing the write  
enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then  
data from the memory location specified by the address pins  
will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW,  
then data from memory will appear on I/O9 to I/O16. See the  
truth table at the back of this data sheet for a complete descrip-  
tion of read and write modes.  
— 1320 mW (max.)  
• Automatic power-down when deselected  
• Independent Control of Upper and Lower bits  
• Available in 44-pin TSOP II and 400-mil SOJ  
Functional Description  
The input/output pins (I/O1 through I/O16) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
The CY7C1021 is a high-performance CMOS static RAM or-  
ganized as 65,536 words by 16 bits. This device has an auto-  
matic power-down feature that significantly reduces power  
consumption when deselected.  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
The CY7C1021 is available in standard 44-pin TSOP Type II  
and 400-mil-wide SOJ packages.  
Logic Block Diagram  
Pin Configuration  
SOJ / TSOP II  
DATA IN DRIVERS  
Top View  
44  
1
A
4
A
5
43  
42  
41  
40  
39  
38  
A
A
2
3
4
5
6
3
6
A
A
2
7
A
A
A
7
6
5
4
OE  
A
1
BHE  
BLE  
I/O  
I/O  
I/O  
A
0
64K x 16  
CE  
A
A
A
A
I/O – I/O  
RAM Array  
512 X 2048  
I/O  
1
8
7
1
16  
37  
36  
35  
34  
33  
3
2
I/O  
I/O  
8
2
3
15  
14  
13  
I/O – I/O  
9
9
16  
10  
11  
12  
13  
I/O  
V
SS  
I/O  
1
0
4
CC  
V
SS  
A
V
V
CC  
32  
I/O  
I/O  
I/O  
5
6
7
8
12  
11  
31  
30  
29  
28  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
I/O  
10  
9
COLUMN DECODER  
WE 17  
NC  
18  
27  
26  
25  
A
A
8
15  
BHE  
19  
A
A
14  
13  
9
10  
11  
WE  
CE  
OE  
A
20  
21  
22  
A
A
A
12  
24  
23  
NC  
NC  
BLE  
1021-2  
Selection Guide  
7C1021-10  
7C1021-12  
7C1021-15  
7C1021-20  
Maximum Access Time (ns)  
10  
220  
5
12  
220  
5
15  
220  
5
20  
220  
5
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
Commercial  
Commercial  
L
0.5  
0.5  
0.5  
0.5  
Shaded areas contain preliminary information.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05054 Rev. **  
Revised August 24, 2001  
1234567...9

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CY7C1021-12ZC CYPRESS

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 		64K x 16 Static RAM
CY7C1021-15 CYPRESS

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 		64K x 16 Static RAM
CY7C1021-15DM CYPRESS

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 		Standard SRAM, 64KX16, 15ns, CMOS, CDIP44, 0.400 INCH, DIP-44
CY7C1021-15DMB CYPRESS

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 		Standard SRAM, 64KX16, 15ns, CMOS, CDIP44, 0.400 INCH, CERDIP-44
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