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CY7B9910-7SIT PDF预览

CY7B9910-7SIT

更新时间: 2024-02-15 05:54:14
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赛普拉斯 - CYPRESS 信息通信管理光电二极管
页数 文件大小 规格书
11页 356K
描述
PLL Based Clock Driver, 7B Series, 8 True Output(s), 0 Inverted Output(s), BICMOS, PDSO24, 0.300 INCH, MO-119, SOIC-24

CY7B9910-7SIT 数据手册

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CY7B9910  
CY7B9920  
Electrical Characteristics  
Over the Operating Range  
CY7B9910  
CY7B9920  
Parameter  
Description  
Test Conditions  
VCC = Min, IOH = –16 mA  
VCC = Min, IOH =–40 mA  
VCC = Min, IOL = 46 mA  
VCC = Min, IOL = 46 mA  
Min  
Max  
Min  
Max  
Unit  
VOH  
Output HIGH Voltage  
2.4  
V
VCC–0.75  
VOL  
Output LOW Voltage  
0.45  
V
0.45  
VCC  
VIH  
VIL  
Input HIGH Voltage  
(REF and FB inputs only)  
2.0  
–0.5  
VCC  
0.8  
VCC  
V
V
1.35  
Input LOW Voltage  
(REF and FB inputs only)  
–0.5  
1.35  
VCC  
VIHH  
VIMM  
VILL  
IIH  
Three Level Input HIGH  
Voltage (Test, FS)[4]  
Min VCC Max  
Min VCC Max  
Min VCC Max  
VCC – 1V  
VCC  
VCC – 1V  
V
Three Level Input MID  
Voltage (Test, FS)[4]  
VCC/2 – VCC/2 +  
500 mV  
VCC/2 –  
500 mV  
VCC/2 +  
500 mV  
V
500 mV  
Three Level Input LOW  
Voltage (Test, FS)[4]  
0.0  
1.0  
0.0  
–500  
–50  
1.0  
V
Input HIGH Leakage Current VCC = Max, VIN = Max  
(REF and FB inputs only)  
10  
10  
μA  
μA  
μA  
μA  
μA  
mA  
mA  
IIL  
Input LOW Leakage Current VCC = Max, VIN = 0.4V  
(REF and FB inputs only)  
–500  
–50  
IIHH  
IIMM  
IILL  
Input HIGH Current  
(Test, FS)  
VIN = VCC  
VIN = VCC/2  
VIN = GND  
200  
50  
200  
50  
Input MID Current  
(Test, FS)  
Input LOW Current  
(Test, FS)  
–200  
–250  
–200  
N/A  
IOS  
Output Short Circuit  
Current[5]  
VCC = Max, VOUT  
= GND (25°C only)  
VCCN = VCCQ = Max All Com’l  
ICCQ  
Operating Current Used by  
Internal Circuitry  
85  
90  
85  
90  
Input  
Selects Open  
Mil/Ind  
ICCN  
Output Buffer Current per  
Output Pair[6]  
VCCN = VCCQ = Max  
14  
19  
mA  
IOUT = 0 mA  
Input Selects Open, fMAX  
PD  
Power Dissipation per  
Output Pair[7]  
VCCN = VCCQ = Max  
78  
104[5]  
mW  
IOUT = 0 mA  
Input Selects Open, fMAX  
Notes  
4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold  
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time  
before all datasheet limits are achieved.  
5. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B9920 outputs are not short circuit  
protected.  
6. Total output current per output pair is approximated by the following expression that includes device current plus load current:  
CY7B9910:  
ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1  
CY7B9920:  
ICCN = [(3.5+.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1  
Where  
F = frequency in MHz  
C = capacitive load in pF  
Z = line impedance in ohms  
N = number of loaded outputs; 0, 1, or 2  
FC = F < C.  
7. Total power dissipation per output pair is approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit:  
CY7B9910:  
PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1  
CY7B9920:  
PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1.See note 3 for variable definition.  
Document Number: 38-07135 Rev. *D  
Page 4 of 11  
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