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CY74FCT841TDIP

更新时间： 2024-11-23 09:43:03

品牌	Logo	应用领域
德州仪器 - TI		锁存器
页数	文件大小	规格书
8页	86K
描述
10-Bit Latch

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数据手册

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CY74FCT841TDIP 数据手册

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modiﬁed to remove devices not offered.

CY54/74FCT841T

SCCS035 - September 1994 - Revised March 2000

10-Bit Latch

• High-speed parallel latches

• Buffered common latch enable input

Features

• Function, pinout, and drive compatible with FCT, F, and

AM29841 logic

• FCT-C speed at 5.5 ns max. (Com’l)

FCT-B speed at 6.5 ns max. (Com’l)

• Reduced V_OH(typically = 3.3V) versions of equivalent

FCT functions

• Edge-rate control circuitry for signiﬁcantly improved

noise characteristics

Functional Description

The FCT841T bus interface latch is designed to eliminate the

extra packages required to buffer existing latches and provide

extra data width for wider address/data paths or buses

carrying parity. The FCT841T is a buffered 10-bit wide version

of the FCT373 function.

The FCT841T high-performance interface is designed for

high-capacitance load drive capability while providing

low-capacitance bus loading at both inputs and outputs.

Outputs are designed for low-capacitance bus loading in the

high impedance state and are designed with a power-off

disable feature to allow for live insertion of boards.

• Power-off disable feature

• Matched rise and fall times

• ESD > 2000V

• Fully compatible with TTL input and output logic levels

• Sink current

64 mA (Com’l),

32 mA (Mil)

Source current 32 mA (Com’l),

12 mA (Mil)

Functional Block Diagram

N- 1

Logic Block Diagram

Pin Configurations

DIP/QSOP/SOIC

Top View

GND

12 3 4 5 6 7 8

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