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CY74FCT373CTQCT PDF预览

CY74FCT373CTQCT

更新时间: 2024-11-25 20:21:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
7页 132K
描述
Bus Driver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.150 INCH, QSOP-20

CY74FCT373CTQCT 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:QSOP包装说明:0.150 INCH, QSOP-20
针数:20Reach Compliance Code:not_compliant
风险等级:5.15Is Samacsys:N
其他特性:POWER OFF DISABLE OUTPUTS TO PERMIT LIVE INSERTION系列:FCT
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.064 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:TAPE AND REEL
电源:5 VProp。Delay @ Nom-Sup:4.2 ns
传播延迟(tpd):5.5 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
宽度:3.9116 mmBase Number Matches:1

CY74FCT373CTQCT 数据手册

 浏览型号CY74FCT373CTQCT的Datasheet PDF文件第2页浏览型号CY74FCT373CTQCT的Datasheet PDF文件第3页浏览型号CY74FCT373CTQCT的Datasheet PDF文件第4页浏览型号CY74FCT373CTQCT的Datasheet PDF文件第5页浏览型号CY74FCT373CTQCT的Datasheet PDF文件第6页浏览型号CY74FCT373CTQCT的Datasheet PDF文件第7页 
1CY54/74FCT573T  
fax id: 7014  
CY54/74FCT373T  
CY54/74FCT573T  
8-Bit Latches  
Features  
Functional Description  
• Function and pinout compatible with FCT, and F logic  
• FCT-C speed at 4.2 ns max. (Com’l),  
FCT-A speed at 5.2 ns max. (Com’l)  
The FCT373T and FCT573T consist of eight latches with  
three-state outputs for bus organized applications. When latch  
enable (LE) is HIGH, the flip-flops appear transparent to the  
data. Data that meets the required set-up times are latched  
when LE transitions from HIGH to LOW. Data appears on the  
bus when the (OE) is LOW. When output enable is HIGH, the  
bus output is in the impedance state. In this mode, data may  
be entered into the latches. The FCT573T is identical to the  
FCT373T except for the flow-through pinout, which simplifies  
board design.  
• Reduced V  
(typically = 3.3V) versions of equivalent  
OH  
FCT functions  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Power-off disable feature  
• ESD > 2000V  
• Matched rise and fall times  
The outputs are designed with a power-off disable feature to  
allow for live insertion of boards.  
• Extended commercial range of 40°C to +85°C  
• Fully compatible with TTL input and output logic levels  
• Sink current  
64 mA (Com’l), 32 mA (Mil)  
Source current 32 mA (Com’l), 12 mA (Mil)  
Logic Block Diagram  
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE  
CP  
D
Q
CP  
D
Q
CP  
D
Q
CP  
D
Q
CP  
D
Q
CP  
D
Q
CP  
D
Q
CP  
D
Q
OE  
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Pin Configurations  
DIP/SOIC/QSOP  
Top View  
DIP/SOIC/QSOP  
Top View  
OE  
1
V
OE  
20  
19  
18  
17  
CC  
1
2
3
4
5
6
V
20  
19  
18  
17  
CC  
D
0
O
2
3
4
0
O
0
O
7
D
1
O
1
D
0
D
7
D
2
O
2
D
1
D
6
FCT573T  
D
3
FCT373T  
O
3
5
16  
O
1
O
6
16  
D
4
O
4
6
15  
14  
O
2
O
5
15  
14  
D
5
O
7
5
D
2
D
7
5
D
6
O
6
8
13  
12  
11  
D
3
D
4
8
13  
12  
11  
D
7
O
9
7
O
3
O
9
4
GND  
10  
LE  
GND  
10  
LE  
Logic Symbol  
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE  
OE  
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
May 1994 – Revised March 18, 1997  

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