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CY74FCT373TSOCR PDF预览

CY74FCT373TSOCR

更新时间： 2024-09-17 19:30:27
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件
页数 文件大小 规格书
12页 463K
描述
FCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, SOIC-20

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CY74FCT373TSOCR 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.06系列：FCT
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：12.8 mm逻辑集成电路类型：BUS DRIVER
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
传播延迟（tpd）：13 ns认证状态：Not Qualified
座面最大高度：2.65 mm最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：7.5 mm
Base Number Matches：1

CY74FCT373TSOCR 数据手册

 浏览型号CY74FCT373TSOCR的Datasheet PDF文件第2页浏览型号CY74FCT373TSOCR的Datasheet PDF文件第3页浏览型号CY74FCT373TSOCR的Datasheet PDF文件第4页浏览型号CY74FCT373TSOCR的Datasheet PDF文件第5页浏览型号CY74FCT373TSOCR的Datasheet PDF文件第6页浏览型号CY74FCT373TSOCR的Datasheet PDF文件第7页 
CY54FCT373T, CY74FCT373T  
8-BIT LATCHES  
WITH 3-STATE OUTPUTS  
SCCS021B – MAY 1994 – REVISED OCTOBER 2001  
CY54FCT373T . . . D PACKAGE  
CY74FCT373T . . . Q OR SO PACKAGE  
(TOP VIEW)  
Function and Pinout Compatible With FCT  
and F Logic  
Reduced V  
of Equivalent FCT Functions  
(Typically = 3.3 V) Versions  
OH  
OE  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
13  
12  
V
CC  
O
O
Edge-Rate Control Circuitry for  
Significantly Improved Noise  
Characteristics  
0
7
D
0
D
7
6
D
D
1
O
O
D
D
O
O
O
1
2
2
3
3
6
5
5
4
I
Supports Partial-Power-Down Mode  
off  
Operation  
D
D
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
O
4
GND 10  
11 LE  
– 1000-V Charged-Device Model (C101)  
Matched Rise and Fall Times  
Fully Compatible With TTL Input and  
Output Logic Levels  
3-State Outputs  
CY54FCT373T  
– 32-mA Output Sink Current  
– 12-mA Output Source Current  
CY74FCT373T  
– 64-mA Output Sink Current  
– 32-mA Output Source Current  
description  
The ’FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the  
latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup  
times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE)  
input is low. When OE is high, the bus output is in the high-impedance state. In this mode, data can be entered  
into the latches.  
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the  
off  
off  
outputs, preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
unless otherwise noted. On all other products, production  
testing of all parameters.  
processing does not necessarily include testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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