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CY74FCT273TSOCE4

更新时间： 2024-11-21 15:42:07
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
13页 469K
描述
D Flip-Flop, FCT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20, GREEN, SOIC-20

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CY74FCT273TSOCE4 技术参数

生命周期：Contact Manufacturer包装说明：SOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.57系列：FCT
JESD-30 代码：R-PDSO-G20长度：12.8 mm
逻辑集成电路类型：D FLIP-FLOP位数：8
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE传播延迟（tpd）：13 ns
座面最大高度：2.65 mm最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：7.5 mm
Base Number Matches：1

CY74FCT273TSOCE4 数据手册

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CY54FCT273T, CY74FCT273T  
8-BIT REGISTERS  
SCCS020A – MARCH 1995 – REVISED OCTOBER 2001  
CY54FCT273T . . . D PACKAGE  
CY74FCT273T . . . Q OR SO PACKAGE  
(TOP VIEW)  
Function, Pinout, and Drive Compatible  
With FCT and F Logic  
Reduced V  
of Equivalent FCT Functions  
(Typically = 3.3 V) Versions  
OH  
MR  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Edge-Rate Control Circuitry for  
Significantly Improved Noise  
Characteristics  
Q
Q
0
7
D
0
D
7
D
D
1
6
Q
1
Q
Q
D
D
I
Supports Partial-Power-Down Mode  
6
5
5
4
off  
Q
Operation  
2
D
D
Q
2
3
3
Matched Rise and Fall Times  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Q
4
GND  
CP  
– 1000-V Charged-Device Model (C101)  
CY54FCT273T . . . L PACKAGE  
(TOP VIEW)  
Fully Compatible With TTL Input and  
Output Logic Levels  
CY54FCT273T  
– 32-mA Output Sink Current  
– 12-mA Output Source Current  
3
2
1 20 19  
18  
D
Q
Q
D
D
D
D
4
5
6
7
8
1
1
2
2
3
7
6
CY74FCT273T  
– 64-mA Output Sink Current  
– 32-mA Output Source Current  
17  
16  
15  
14  
Q
Q
D
6
5
5
description  
9 10 11 12 13  
The ’FCT273T devices consist of eight  
edge-triggered D-type flip-flops with individual  
D inputs and  
Q
outputs. The common  
buffered-clock (CP) and master-reset (MR) inputs  
load and reset all flip-flops simultaneously. These  
devices are edge-triggered registers. The state of  
each D input (one setup time before the  
low-to-high clock transition) is transferred to the  
corresponding flip-flop’s Q output. All outputs are  
forced low by a low logic level on the MR input.  
This  
device  
is  
fully  
specified  
for  
partial-power-downapplicationsusingI . TheI  
off  
off  
circuitry disables the outputs, preventing  
damaging current backflow through the device  
when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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