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CY74FCT138ATPC PDF预览

CY74FCT138ATPC

更新时间: 2024-11-08 21:54:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 解码器
页数 文件大小 规格书
6页 158K
描述
1-of-8 Decoder

CY74FCT138ATPC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.44其他特性:3 ENABLE INPUTS
系列:FCTJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.177 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.064 A功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:5.8 ns
传播延迟(tpd):5.8 ns认证状态:Not Qualified
座面最大高度:4.826 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

CY74FCT138ATPC 数据手册

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1CY54/74FCT138T  
fax id: 7013  
CY54/74FCT138T  
1-of-8 Decoder  
Source current 32 mA (Com’l),  
Features  
12 mA (Mil)  
Function, pinout, and drive compatible with FCT and  
F logic  
Dual 1-of-8 decoder with enables  
Functional Description  
FCT-C speed at 5.0 ns max. (Com’l),  
FCT-A speed at 5.8 ns max. (Com’l)  
The FCT138T is a 1-of-8 decoder. The FCT138T accepts  
three binary weighted inputs (A , A , A ) and, when enabled,  
Reduced V  
(typically = 3.3V) versions of equivalent  
OH  
0
1
2
FCT functions  
provides eight mutually exclusive active LOW outputs  
(O –O ). The FCT138T features three enable inputs, two  
Edge-rate control circuitry for significantly improved  
noise characteristics  
Power-off disable feature  
ESD > 2000V  
Matched rise and fall times  
Fully compatible with TTL input and output logic levels  
Extended commercial range of 40°C to +85°C  
0
7
active LOW (E , E ) and one active HIGH (E ).  
1
2
3
All inputs will be HIGH unless E and E are LOW and E is  
1
2
3
HIGH. This multiple enable function allows easy parallel  
expansion of the device to a 1-of-32 (5 lines to 32 lines)  
decoder with just four FCT138T devices and one inverter.  
The outputs are designed with a power-off disable feature to  
allow for live insertion of boards.  
• Sink current  
64 mA (Com’l),  
32 mA (Mil)  
Logic Block Diagram  
Pin Configurations  
E
1
E E  
2 3  
LCC  
A
2
A
1
A
0
DIP/SOIC/QSOP  
Top View  
Top View  
A
1
V
0
16  
15  
14  
13  
12  
CC  
7
6 5 4  
8
A
1
2
3
4
O
O
O
O
O
O
O
O
7
A
1
0
1
2
3
4
5
6
9
3
2
A
2
GND  
NC  
A
0
10  
11  
E
1
NC  
V
1
E
2
O
6
CC  
12  
13  
20  
19  
5
6
7
8
O
0
O
5
E
3
11  
10  
9
15 16 17 18  
14  
O
7
GND  
FCT138T–2  
FCT138T–3  
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
FCT138T–1  
Pin Description  
Name  
Description  
A
Address Inputs  
E E  
Enable Inputs (Active LOW)  
Enable Input (Active HIGH)  
Outputs  
1
2
E
3
O
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
May 1994 – Revised March 17, 1997  

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