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CY62128DV30LL-55SI PDF预览

CY62128DV30LL-55SI

更新时间： 2024-10-01 22:24:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 198K
描述
1 Mb (128K x 8) Static RAM

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中文翻译

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CY62128DV30LL-55SI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：0.450 INCH, SOIC-32
针数：32Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.24
最长访问时间：55 nsI/O 类型：COMMON
JESD-30 代码：R-PDSO-G32JESD-609代码：e0
长度：20.4465 mm内存密度：1048576 bit
内存集成电路类型：STANDARD SRAM内存宽度：8
湿度敏感等级：3功能数量：1
端子数量：32字数：131072 words
字数代码：128000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX8输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP32,.56封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：PARALLEL
峰值回流温度（摄氏度）：225电源：2.5/3.3 V
认证状态：Not Qualified座面最大高度：2.997 mm
最大待机电流：0.000003 A最小待机电流：1.5 V
子类别：SRAMs最大压摆率：0.01 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.2 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：11.303 mm
Base Number Matches：1

CY62128DV30LL-55SI 数据手册

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CY62128DV30  
MoBL  
1 Mb (128K x 8) Static RAM  
power consumption by 90% when addresses are not toggling.  
The device can be put into standby mode reducing power con-  
sumption by more than 99% when deselected Chip Enable 1  
(CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output  
pins (I/O0 through I/O7) are placed in a high-impedance state  
when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable  
2 (CE2) LOW, outputs are disabled (OE HIGH), or during a  
write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2  
(CE2) HIGH and Write Enable (WE) LOW).  
Features  
• Very high speed: 55 and 70 ns  
• Wide voltage range: 2.2V to 3.6V  
• Pin compatible with CY62128V  
• Ultra-low active power  
— Typical active current: 0.85 mA @ f = 1 MHz  
— Typical active current: 5 mA @ f = fMAX  
• Ultra-low standby power  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) LOW with Chip Enable 2 (CE2) HIGH and Write En-  
able(WE) LOW. Data on the eight I/O pins is then written into  
the location specified on the Address pin (A0 thro. A16).  
• Easy memory expansion with CE1, CE2, and OE  
features  
• Automatic power-down when deselected  
• Packages offered in a 32-lead SOIC, a 32-lead TSOP, a  
32-lead Short TSOP, and a 32-lead Reverse TSOP  
Reading from the device is accomplished by taking Chip En-  
able 1 (CE1) LOW with Chip Enable 2 (CE2) HIGH and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.  
Under these conditions, the contents of the memory location  
specified by the address pins will appear on the I/O pins.  
Functional Description[1]  
The CY62128DV30 is a high-performance CMOS static RAM  
organized as 128K words by 8 bits. This device features ad-  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life(MoBL®) in portable  
applications such as cellular telephones. The device also has  
an automatic power-down feature that significantly reduces  
The eight input/output pins (I/Oo through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH) or  
during a write operation (CE1 LOW, CE2 HIGH), and WE  
LOW).  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
Data in Drivers  
A
A
A
A
A
A
0
1
2
3
4
5
6
7
A
128K x 8  
ARRAY  
A
A
A
A10  
A11  
8
9
Power-  
down  
CE  
CE  
COLUMN  
DECODER  
1
2
I/O  
WE  
OE  
7
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05231 Rev. *C  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised August 29, 2003  
1234567...11

中文翻译

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CY62128DV30LL-55SI 替代型号

型号 品牌 替代类型 描述 数据表
CY62128DV30LL-55SXIT CYPRESS

功能相似

 Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62128DV30LL-55SXI CYPRESS

功能相似

 1-Mb (128K x 8) Static RAM
CY62128DV30L-55SI CYPRESS

功能相似

 1 Mb (128K x 8) Static RAM

与CY62128DV30LL-55SI相关器件

型号 品牌 获取价格 描述 数据表
CY62128DV30LL-55SXI CYPRESS

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 		1-Mb (128K x 8) Static RAM
CY62128DV30LL-55SXIT CYPRESS

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 		Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62128DV30LL-55ZAI CYPRESS

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 		1 Mb (128K x 8) Static RAM
CY62128DV30LL-55ZAI ROCHESTER

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 		128KX8 STANDARD SRAM, 55ns, PDSO32, 8 X 13.40 MM, STSOP-32
CY62128DV30LL-55ZAIT ROCHESTER

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 		128KX8 STANDARD SRAM, 55ns, PDSO32, 8 X 13.40 MM, STSOP-32
CY62128DV30LL-55ZAXI CYPRESS

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 		1-Mb (128K x 8) Static RAM
CY62128DV30LL-55ZAXIT ROCHESTER

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 		128KX8 STANDARD SRAM, 55ns, PDSO32, 8 X 13.40 MM, LEAD FREE, STSOP-32
CY62128DV30LL-55ZAXIT CYPRESS

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 		Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, 8 X 13.40 MM, LEAD FREE, STSOP-32
CY62128DV30LL-55ZI CYPRESS

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 		1 Mb (128K x 8) Static RAM
CY62128DV30LL-55ZIT CYPRESS

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 		Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32

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