Datasheet > CY62128BLL-55ZIT

CY62128BLL-55ZIT

更新时间： 2024-11-10 08:38:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器光电二极管
页数	文件大小	规格书
11页	286K
描述
Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32

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CY62128BLL-55ZIT 数据手册

CY62128B

MoBL^®

1-Mbit (128K x 8) Static RAM

Features

Functional Description^[1]

• Temperature Ranges

The CY62128B is a high-performance CMOS static RAM

organized as 131,072 words by 8 bits. Easy memory

expansion is provided by an active LOW Chip Enable (CE₁),

an active HIGH Chip Enable (CE₂), an active LOW Output

Enable (OE), and three-state drivers. This device has an

automatic power-down feature that reduces power

consumption by more than 75% when deselected.

—Commercial: 0°C to 70°C

— Industrial: –40°C to 85°C

— Automotive: –40°C to 125°C

• 4.5V–5.5V operation

• CMOS for optimum speed/power

Writing to the device is accomplished by taking Chip Enable

One (CE₁) and Write Enable (WE) inputs LOW and Chip

Enable Two (CE₂) input HIGH. Data on the eight I/O pins (I/O₀

through I/O₇) is then written into the location specified on the

address pins (A₀through A₁₆).

• Low active power

(70 ns, LL version, Commercial, Industrial)

— 82.5 mW (max.) (15 mA)

• Low standby power

(70 ns, LL version, Commercial, Industrial)

Reading from the device is accomplished by taking Chip

Enable One (CE₁) and Output Enable (OE) LOW while forcing

Write Enable (WE) and Chip Enable Two (CE₂) HIGH. Under

these conditions, the contents of the memory location

specified by the address pins will appear on the I/O pins.

— 110 µW (max.) (15 µA)

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE₁, CE₂, and OE options

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE₁

HIGH or CE₂LOW), the outputs are disabled (OE HIGH), or

during a write operation (CE₁LOW, CE₂HIGH, and WE LOW).

The CY62128B is available in a standard 450-mil-wide SOIC,

32-pin TSOP type I and STSOP packages.

Logic Block Diagram

I/O

INPUT BUFFER

I/O

512x256x8

ARRAY

I/O

POWER

DOWN

COLUMN

DECODER

Note:

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05300 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised March 7, 2005

12 3 4 5 6 7...11

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与CY62128BLL-55ZIT相关器件

型号	品牌	获取价格	描述	数据表
CY62128BLL-55ZRC	CYPRESS	获取价格	Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, REVERSE, TSOP1-32
CY62128BLL-55ZRCT	CYPRESS	获取价格	暂无描述
CY62128BLL-55ZRI	CYPRESS	获取价格	128K x 8 Static RAM
CY62128BLL-55ZRIT	ROCHESTER	获取价格	128KX8 STANDARD SRAM, 55ns, PDSO32, REVERSE, TSOP1-32
CY62128BLL-55ZXI	ROCHESTER	获取价格	128KX8 STANDARD SRAM, 55ns, PDSO32, 8 X 20 MM, LEAD FREE, TSOP1-32
CY62128BLL-55ZXI	CYPRESS	获取价格	128K x 8 Static RAM
CY62128BLL-70SC	CYPRESS	获取价格	128K x 8 Static RAM
CY62128BLL-70SC	ROCHESTER	获取价格	128KX8 STANDARD SRAM, 70ns, PDSO32, 0.450 INCH, SOIC-32
CY62128BLL-70SCT	ROCHESTER	获取价格	128KX8 STANDARD SRAM, 70ns, PDSO32, 0.450 INCH, SOIC-32
CY62128BLL-70SCT	CYPRESS	获取价格	Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 0.450 INCH, SOIC-32

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