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CY39100V484-125BBI PDF预览

CY39100V484-125BBI

更新时间： 2024-01-31 12:36:06
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 可编程逻辑输入元件
页数 文件大小 规格书
86页 1209K
描述
CPLDs at FPGA Densities

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CY39100V484-125BBI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：LBGA,
针数：484Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.84
Is Samacsys：N其他特性：CAN ALSO OPERATE WITH 3.3V SUPPLY
JESD-30 代码：S-PBGA-B484JESD-609代码：e0
长度：23 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：302
端子数量：484最高工作温度：85 °C
最低工作温度：-40 °C组织：0 DEDICATED INPUTS, 302 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE峰值回流温度（摄氏度）：220
可编程逻辑类型：LOADABLE PLD传播延迟：10 ns
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压：2.7 V最小供电电压：2.3 V
标称供电电压：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：23 mm
Base Number Matches：1

CY39100V484-125BBI 数据手册

 浏览型号CY39100V484-125BBI的Datasheet PDF文件第2页浏览型号CY39100V484-125BBI的Datasheet PDF文件第3页浏览型号CY39100V484-125BBI的Datasheet PDF文件第4页浏览型号CY39100V484-125BBI的Datasheet PDF文件第6页浏览型号CY39100V484-125BBI的Datasheet PDF文件第7页浏览型号CY39100V484-125BBI的Datasheet PDF文件第8页 
Delta39K™ ISR™  
CPLD Family  
Clock Inputs  
GCLK[3:0]  
4
Logic  
Block  
0
Logic  
Block  
7
36  
16  
36  
16  
Logic  
Block  
1
Logic  
Block  
6
36  
16  
36  
16  
Logic  
Block  
2
Logic  
Block  
5
36  
16  
36  
16  
PIM  
Logic  
Block  
3
Logic  
Block  
4
36  
16  
36  
16  
Cluster  
Memory  
0
Cluster  
Memory  
1
25  
8
25  
8
CC = Carry Chain  
64 Inputs From  
Vertical Routing  
Channel  
64 Inputs From  
Horizontal Routing  
Channel  
144 Outputs to  
Horizontal and Vertical  
cluster-to-channel PIMs  
Figure 3. Delta39K Logic Block Cluster Diagram  
Logic Block  
provides two important capabilities without affecting perfor-  
mance: product term steering and product term sharing.  
The LB is the basic building block of the Delta39K architecture.  
It consists of a product term array, an intelligent product-term  
allocator, and 16 macrocells.  
Product Term Steering  
Product term steering is the process of assigning product  
terms to macrocells as needed. For example, if one macrocell  
requires ten product terms while another needs just three, the  
product term allocator will “steer” ten product terms to one  
macrocell and three to the other. On Delta39K devices,  
product terms are steered on an individual basis. Any number  
between 1 and 16 product terms can be steered to any  
macrocell.  
Product Term Array  
Each logic block features a 72 x 83 programmable product  
term array. This array accepts 36 inputs from the PIM. These  
inputs originate from device pins and macrocell feedbacks as  
well as cluster memory and channel memory feedbacks.  
Active LOW and active HIGH versions of each of these inputs  
are generated to create the full 72-input field. The 83 product  
terms in the array can be created from any of the 72 inputs.  
Product Term Sharing  
Of the 83 product terms, 80 are for general-purpose use for  
the 16 macrocells in the logic block. Two of the remaining three  
product terms in the logic block are used as asynchronous set  
and asynchronous reset product terms. The final product term  
is the Product Term clock (PTCLK) and is shared by all 16  
macrocells within a logic block.  
Product term sharing is the process of using the same product  
term among multiple macrocells. For example, if more than  
one function has one or more product terms in its equation that  
are common to other functions, those product terms are only  
programmed once. The Delta39K product term allocator  
allows sharing across groups of four macrocells in a variable  
fashion. The software automatically takes advantage of this  
capability so that the user does not have to intervene.  
Product Term Allocator  
Through the product term allocator, Warp software automati-  
cally distributes the 80 product terms as needed among the 16  
macrocells in the logic block. The product term allocator  
Note that neither product term sharing nor product term  
steering have any effect on the speed of the product. All  
steering and sharing configurations have been incorporated in  
the timing specifications for the Delta39K devices.  
.
Document #: 38-03039 Rev. *H  
Page 5 of 86  
12345678...86

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CY39100V484-125MBI CYPRESS CPLDs at FPGA Densities

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CY39100V484A-125BBC CYPRESS Loadable PLD, 10ns, 1536-Cell, CMOS, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBG

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CY39100V484B-125BBC CYPRESS Loadable PLD, 10ns, 1536-Cell, CMOS, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA

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