Datasheet > CY39100V256-181MGC

CY39100V256-181MGC

更新时间： 2022-11-25 15:01:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
86页	1209K
描述
CPLDs at FPGA Densities

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY39100V256-181MGC 数据手册

浏览型号CY39100V256-181MGC的Datasheet PDF文件第1页

浏览型号CY39100V256-181MGC的Datasheet PDF文件第2页

浏览型号CY39100V256-181MGC的Datasheet PDF文件第4页

浏览型号CY39100V256-181MGC的Datasheet PDF文件第5页

浏览型号CY39100V256-181MGC的Datasheet PDF文件第6页

浏览型号CY39100V256-181MGC的Datasheet PDF文件第7页

Delta39K™ ISR™

CPLD Family

PLL and Clock MUX

GCLK[3:0]

GCTL[3:0]

I/O Bank 7

I/O Bank 6

GCLK[3:0]

LB 0

LB 1

LB 2

LB 3

LB 7

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 7

LB 6

LB 5

LB 4

LB 0

LB 7

LB 6

LB 5

LB 4

LB 1

LB 2

LB 3

LB 1

LB 2

LB 3

Channel

RAM

Channel

RAM

Channel

RAM

Channel

RAM

PIM

LB 5

LB 4

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

GCLK[3:0]

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

Channel

RAM

Channel

RAM

Channel

RAM

Channel

RAM

PIM

LB 5

LB 4

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

GCLK[3:0]

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

Channel

RAM

Channel

RAM

Channel

RAM

Channel

RAM

PIM

LB 5

LB 4

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

I/O Bank 2

I/O Bank 3

Figure 1. Delta39K100 Block Diagram (Three Rows × Four Columns) with I/O Bank Structure

The architecture is based on Logic Block Clusters (LBC) that

General Description

are connected by Horizontal and Vertical (H and V) routing

channels. Each LBC features eight individual Logic Blocks

(LB) and two cluster memory blocks. Adjacent to each LBC is

a channel memory block, which can be accessed directly from

the I/O pins. Both types of memory blocks are highly config-

urable and can be cascaded in width and depth. See Figure 1

for a block diagram of the Delta39K architecture.

The Delta39K family, based on a 0.18-mm, six-layer metal

CMOS logic process, offers a wide range of high-density

solutions at unparalleled system performance. The Delta39K

family is designed to combine the high speed, predictable

timing, and ease of use of CPLDs with the high densities and

low power of FPGAs. With devices ranging from 30,000 to

200,000 usable gates, the family features devices ten times

the size of previously available CPLDs. Even at these large

densities, the Delta39K family is fast enough to implement a

fully synthesizable 64-bit, 66-MHz PCI core.

All the members of the Delta39K family have Cypress’s highly

regarded In-System Reprogrammability (ISR) feature, which

simplifies both design and manufacturing flows, thereby

reducing costs. The ISR feature provides the ability to recon-

Document #: 38-03039 Rev. *H

Page 3 of 86

1 234 5 6 7...86

下载PDF

与CY39100V256-181MGC相关器件

型号	品牌	描述	获取价格	数据表
CY39100V256-181NC	CYPRESS	CPLDs at FPGA Densities	获取价格
CY39100V256-200MGC	CYPRESS	CPLDs at FPGA Densities	获取价格
CY39100V256-233MGC	CYPRESS	CPLDs at FPGA Densities	获取价格
CY39100V256-233MGI	CYPRESS	CPLDs at FPGA Densities	获取价格
CY39100V256-233NTC	CYPRESS	CPLDs at FPGA Densities	获取价格
CY39100V256-83BBI	CYPRESS	Loadable PLD, 15ns, CMOS, PBGA256, 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-256	获取价格