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CY28551LFXC

更新时间： 2024-02-23 01:54:17

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		晶体时钟发生器外围集成电路
页数	文件大小	规格书
30页	662K
描述
Universal Clock Generator for Intel, VIA, and SIS㈢

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中文翻译

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数据手册

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CY28551LFXC 数据手册

CY28551

UniversalClockGeneratorforIntel, VIA,

and SIS^®

• Dynamic Frequency Control

• Dial-A-Frequency^®

Features

• Compliant to Intel^®CK505

• WatchDog Timer

• Selectable CPU clock buffer type for Intel P4 or K8 selection

• Selectable CPU frequencies

• Two Independent Overclocking PLLs

• Low-voltage frequency select input

• I²C support with readback capabilities

• Universal clock to support Intel, SiS and VIA platform

• 0.7V Differential CPU clock for Intel CPU

• 3.3V Differential CPU clock for AMD K8

• 100 MHz differential SRC clocks

• 96 MHz differential dot clock

• Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• 3.3V Power supply

• 64-pin QFN package

• 133 MHz Link clock

CPU SRC SATA

x 2 x 8 x1

PCI

x 7

REF LINK

x 3 x2

DOT96

x 1

24_48M

48M

x 1

• 48 MHz USB clock

• 33 MHz PCI clocks

Block Diagram

Pin Configuration

VDD_REF

Xin

Xout

14.318MHz

Crystal

REF[2:0]

PLL Reference

VDD_CPU

CPUT[1:0]

CPUC[1:0]

VDD_PCIEX

Divider

PLL1

CPU

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

PCIET[8:1]

PCIEC[8:1]

DOC[2:1]

FS[D:A]

PCI6_F

48 VDDREF

47 SCLK

VDD48

**SEL24_48 / 24_48M

**SEL1/48M

VDD_SATA

SEL_P4_K8

46 SDATA

PCIET0 /SATAT

PCIEC0/SATAC

45 VTTPWRG#/PD

44 CPUT0

VSS48

PLL2

PCIEX

Divider

43 CPUC0

42 VDDCPU

41 CPUT1

VDDDOT

LINK0/DOT96T/SATAT

LINK1/DOT96C/SATAC

VSSDOT

Multiplexer

Controller

VDD_DOT

DOT96T/SATAT/LINK0

DOT96C/SATAC/LINK1

CY28551

40 CPUC1

39 VSSCPU

SEL[1:0]

VDDSATA 10

SATAT/PCIEXT0 11

SATAC/PCIEXC0 12

VSSSATA 13

**DOC2

37 VSSA

36 VDDA

VDD_PCI

PCI[6:0]

PCIEXT1 14

PCIEXT8/CPU_STP#

PCIEXC8/PCI_STP#

Divider

PLL3

SATA

PCIEXC1 15

VSSPCIE 16

33 VDDPCIE

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

PLL4

Fixed

VDD_48

48M

TPWR_GD#/PD

SEL24_48

24_48M

* Indicates internal pull up

** indicates internal pull down

RESET_I#

SDATA

SCLK

I2C

Logic

WDT

SRESET#

Cypress Semiconductor Corporation

Document #: 001-05675 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 26, 2006

12 3 4 5 6 7...30

中文翻译

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