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CY28RS400 PDF预览

CY28RS400

更新时间: 2024-01-30 09:23:57
品牌 Logo 应用领域
SPECTRALINEAR 时钟发生器
页数 文件大小 规格书
18页 179K
描述
Clock Generator for ATI RS400 Chipset

CY28RS400 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:TSSOP包装说明:6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56
针数:56Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.29Is Samacsys:N
JESD-30 代码:R-PDSO-G56JESD-609代码:e4
长度:13.9955 mm湿度敏感等级:3
端子数量:56最高工作温度:70 °C
最低工作温度:最大输出时钟频率:266 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:14.31818 MHz
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Clock Generators最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:6.096 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

CY28RS400 数据手册

 浏览型号CY28RS400的Datasheet PDF文件第2页浏览型号CY28RS400的Datasheet PDF文件第3页浏览型号CY28RS400的Datasheet PDF文件第4页浏览型号CY28RS400的Datasheet PDF文件第5页浏览型号CY28RS400的Datasheet PDF文件第6页浏览型号CY28RS400的Datasheet PDF文件第7页 
CY28RS400  
Clock Generator for ATI£ꢀ RS400 Chipset  
• Low-voltage frequency select input  
• I2C support with readback capabilities  
Features  
• Supports Intel£ CPU  
• Ideal Lexmark Spread Spectrum profile for maximum  
electromagnetic interference (EMI) reduction  
• Selectable CPU frequencies  
• Differential CPU clock pairs  
• 100 MHz differential SRC clocks  
• 48 MHz USB clock  
• 3.3V power supply  
• 56-pin SSOP and TSSOP packages  
CPU  
x3  
SRC  
x8  
PCI  
x1  
REF  
x 3  
USB_48  
x 1  
• 33 MHz PCI clock  
Block Diagram  
Pin Configuration  
VDD_REF  
REF[0:2]  
Xin  
XOUT  
VDD_48  
USB_48  
VSS_48  
1
2
3
4
5
6
7
8
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
VDD_REF  
XIN  
XTAL  
OSC  
VSS_REF  
REF0/FSA  
REF1/FSB  
REF2  
XOUT  
PLL Ref Freq  
VDD_CPU  
CPUT[0:2], CPUC[0:2],  
Divider  
CPU_STP#  
PLL1  
Network  
CLKREQ[0:1]#  
VDD_SRC  
VTT_PWRGD#/PD  
VDD_PCI  
SRCT[0:5],SRCC[0:5]  
SCLK  
SDATA  
FSC  
PCI0/409_410  
VSS_PCI  
CPU_STOP#  
CPUT0  
FS_[C:A]  
VTT_PWRGD#  
VDD_SRCS  
SRCST[0:1],SRCSC[0:1]  
9
IREF  
CLKREQ#0  
CLKREQ#1  
SRCT5  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
VDD_PCI  
PCI  
CPUC0  
VDD_CPU  
VSS_CPU  
CPUT1  
CPUC1  
CPUT2  
CPUC2  
VDDA  
VSSA  
IREF  
SRCC5  
VDD_SRC  
VSS_SRC  
SRCT4  
PD  
VDD_48 MHz  
USB_48  
SRCC4  
SRCT3  
SRCC3  
PLL2  
VSS_SRC  
VDD_SRC  
SRCT2  
VSS_SRC1  
VDD_SRC1  
SRCT0  
SRCC2  
SRCT1  
SRCC1  
SRCC0  
VDD_SRCS  
VSS_SRCS  
SRCST0  
SRCSC0  
VSS_SRC  
SRCST1  
SRCSC1  
2
SDATA  
SCLK  
I C  
Logic  
56 SSOP/TSSOP  
Rev 1.0, November 22, 2006  
2200 Laurelwood Road, Santa Clara, CA 95054  
Page 1 of 18  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com  

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