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CY27C512-200ZC PDF预览

CY27C512-200ZC

更新时间: 2024-11-09 19:38:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS OTP只读存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 202K
描述
OTP ROM, 64KX8, 200ns, CMOS, PDSO28, TSOP-28

CY27C512-200ZC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP包装说明:TSOP-28
针数:28Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.05最长访问时间:200 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G28
JESD-609代码:e0内存密度:524288 bit
内存集成电路类型:OTP ROM内存宽度:8
功能数量:1端子数量:28
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:TSSOP28,.53,22
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
最大待机电流:0.015 A子类别:OTP ROMs
最大压摆率:0.04 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.55 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

CY27C512-200ZC 数据手册

 浏览型号CY27C512-200ZC的Datasheet PDF文件第2页浏览型号CY27C512-200ZC的Datasheet PDF文件第3页浏览型号CY27C512-200ZC的Datasheet PDF文件第4页浏览型号CY27C512-200ZC的Datasheet PDF文件第5页浏览型号CY27C512-200ZC的Datasheet PDF文件第6页浏览型号CY27C512-200ZC的Datasheet PDF文件第7页 
1CY27C512  
fax id: 3019  
CY27C512  
64K x 8 CMOS EPROM  
is also available in windowed packages (28-pin hermetic DIP  
and and 32-pin LCC) which allow the device to be erased with  
UV light for 100% reprogrammability.  
Features  
• Very Fast Read Access Time: (45 - 200 ns)  
• 5V ± 10% Power Supply  
• Capable of withstanding >2001V ESD  
• Latch-up Protection up to 200mA  
Two line control functions to prevent bus contention  
• Standard JEDEC Packages  
The CY27C512 is equipped with a power-down chip enable  
(CE) input and output enable (OE) to prevent bus contention.  
When CE is deasserted, the device powers down to a  
low-power stand-by mode. The OE pin three-states the out-  
puts without putting the device into stand-by mode. While CE  
offers lower power, OE provides a more rapid transition to and  
from three-stated outputs.  
— 32-pin PLCC  
— 28-pin TSOP  
The memory cells utilize proven EPROM floating-gate  
technology and byte-wide intelligent programming algorithms.  
The EPROM cell requires only 12.75V for the supervoltage  
and low programming current allows for gang programming.  
The device allows for each memory location to be tested  
100%, because each location is written to, erased, and  
repeatedly exercised prior to encapsulation. Each device is  
also tested for AC performance to guarantee that the product  
will meet DC and AC specification limits after customer  
programming.  
— 28-pin, 600-mil plastic DIP  
— 32-pin, hermetic LCC  
— 28-pin, 600-mil hermetic DIP  
• Available in Commercial, Industrial, and Military  
Temperature Ranges  
Functional Description  
The CY27C512 is a high-performance, 512-Kbit ultraviolet  
erasable programmable read-only memory (EPROM)  
organized as 64 Kbytes by 8 bits. It is available in  
JEDEC-standard, one-time programmable (OTP), 32-pin  
PLCC and 28-pin PDIP and TSOP packages. The CY27C512  
The CY27C512 is read by asserting both the CE and the OE  
inputs. The contents of the memory location selected by the  
address on inputs A A will appear at the outputs O O .  
15  
0
7
0
Logic Block Diagram  
A0  
A1  
O 0  
A2  
PROGRAMMABLE  
O 1  
A3  
A4  
A5  
ARRAY  
O 2  
O 3  
DATA OUTPUTS  
ADDRESS INPUTS  
A6  
MULTIPLEXER  
A7  
A8  
ADDRESS  
DECODER  
O 4  
O 5  
A9  
A10  
A11  
A 12  
A13  
POWER DOWN  
O 6  
O 7  
A14  
A15  
CE  
OE  
OUTPUT ENABLE  
DECODER  
C512–1  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
April 1995 Revised- March 19, 1997  

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