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CY25702JXCZZZZ PDF预览

CY25702JXCZZZZ

更新时间: 2024-11-24 22:06:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 振荡器晶体振荡器时钟发生器微控制器和处理器外围集成电路石英晶振光电二极管
页数 文件大小 规格书
7页 126K
描述
Programmable High-Frequency Crystal Oscillator (XO)

CY25702JXCZZZZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOJ,针数:4
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.8
其他特性:ALSO OPERATES AT 3V SUPPLYJESD-30 代码:R-PDSO-J4
JESD-609代码:e3/e4长度:10.2 mm
端子数量:4最高工作温度:70 °C
最低工作温度:-20 °C最大输出时钟频率:125 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:2.7 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN/NICKEL PALLADIUM GOLD
端子形式:J BEND端子节距:5.08 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

CY25702JXCZZZZ 数据手册

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CY25702  
Programmable High-Frequency Crystal Oscillator (XO)  
Features  
Benefits  
• Programmable High-frequency Crystal Oscillator (XO)  
• Wide output (CLK) range from:  
— 1.0 to 125 MHz (VDD = 5.0V)  
— 1.0 to 90 MHz (VDD = 3.3V)  
• Integrated phase-locked loop (PLL)  
• Low cycle-to-cycle Jitter  
• 3.3/5.0V operation  
• Output Enable function  
• Power-down function  
• Refer to CY25701 for SSCG function  
• Lead-free package  
• Eliminates the need for external crystal oscillator.  
• Internal PLL to generate up to 125-MHz output.  
• Suitable for most PC, consumer and networking  
applications.  
• Application compatibility in standard and low-power  
systems.  
• CY25701 can be used as a direct replacement in 3.3V  
applications if Spread Spectrum Clock (SSC) is  
required for EMI reduction without any PCB  
modification.  
• In-house programming of samples and prototype  
quantities is available using the CY3672 programming  
kit and CY36xx socket adapter. Sample and production  
quantitiesareavailablethroughCypress’svalue-added  
distribution partners.  
Pin Configuration  
Logic Block Diagram  
CY25702  
4-pin Plastic SMD  
RFB  
PLL  
1
2
OE/PD#  
VSS  
VDD  
CLK  
4
3
CXIN  
OUTPUT  
DIVIDERS  
and  
PROGRAMMABLE  
CONFIGURATION  
3
CLK  
MUX  
CXOUT  
1
OE/PD#  
4
2
VDD  
VSS  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07721 Rev. **  
Revised December 09, 2004  

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