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CY25200

更新时间: 2024-09-29 22:40:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器
页数 文件大小 规格书
11页 281K
描述
Programmable Spread Spectrum Clock Generator for EMI Reduction

CY25200 数据手册

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CY25200  
Programmable Spread Spectrum  
Clock Generator for EMI Reduction  
Benefits  
Features  
• Wide operating output (SSCLK) frequency range  
— 3–200 MHz  
• Suitable for most PC peripherals, networking, and consum-  
er applications.  
• Provides wide range of spread percentages for maximum  
• Programmable spread spectrum with nominal 31.5-kHz  
EMI reduction, to meet regulatory agency Electro Magnetic  
Compliance (EMC) requirements. Reduces development  
and manufacturing costs and time-to-market.  
modulation frequency.  
• Center spread: ±0.25% to ±2.5%  
• Down spread: –0.5% to –5.0%  
• Input frequency range:  
• Eliminates the need for expensive and difficult to use higher  
order crystals.  
• Internal PLL generates up to 200 MHz outputs, and can  
generate custom frequencies from an external crystal or a  
driven source.  
— External crystal: 8–30 MHz fundamental crystals  
— External reference: 8–166 MHz Clock  
• Integrated phase-locked loop (PLL)  
• Programmable crystal load capacitor tuning array  
• Low cycle-to-cycle Jitter  
• 3.3V operation with 2.5V output clock drive option  
• Spread spectrum On/Off function  
• Power-down or Output Enable function  
• Output frequency select option  
• Enables fine-tuning of output clock frequency by adjusting  
C
Load of the crystal. Eliminates the need for external CLoad  
capacitors.  
• Application compatibility in standard and low-power sys-  
tems.  
• Provides ability to enable or disable spread spectrum with  
an external pin.  
• Enables low-power state or output clocks to High-Z state.  
Logic Block Diagram  
SSCLK1  
7
Divider  
Bank 1  
8
SSCLK2  
Output  
Select  
Matrix  
9
SSCLK3  
SSCLK4  
XIN/CLKIN  
XOUT  
1
Q
Φ
OSC.  
12  
VCO  
16  
P
C
XOUT  
C
Divider  
Bank 2  
XIN  
PLL  
14  
15  
SSCLK5/REFOUT/CP2  
SSCLK6/REFOUT/CP3  
6
2
3
5
11  
4
10  
13  
AVSS VSS  
VDD  
AVDD  
VDDL VSSL  
CP0 CP1  
Pin Configuration  
XOUT  
1
2
3
4
5
6
16  
15  
14  
13  
12  
XIN  
VDD  
AVDD  
CP0  
SSCLK6/REFOUT/CP3  
SSCLK5/REFOUT/CP2  
VSS  
AVSS  
VSSL  
SSCLK1  
SSCLK2  
SSCLK4  
VDDL  
11  
10  
9
7
8
CP1  
SSCLK3  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07633 Rev. *A  
Revised April 22, 2004  

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