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CY25200KZXC-XXXWT

更新时间： 2024-09-30 19:33:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
17页 595K
描述
200MHz, OTHER CLOCK GENERATOR, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16

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CY25200KZXC-XXXWT 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：TSSOP包装说明：TSSOP,
针数：16Reach Compliance Code：compliant
风险等级：5.3JESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：5 mm
湿度敏感等级：3端子数量：16
最高工作温度：70 °C最低工作温度：
最大输出时钟频率：200 MHz封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
主时钟/晶体标称频率：166 MHz认证状态：Not Qualified
座面最大高度：1.1 mm最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：20宽度：4.4 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

CY25200KZXC-XXXWT 数据手册

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CY25200  
Programmable Spread Spectrum  
Clock Generator for EMI Reduction  
Programmable Spread Spectrum Clock Generator for EMI Reduction  
Features  
Description  
■ Wide Operating Output (SSCLK) Frequency Range  
❐ 3 to 200 MHz  
The CY25200 is a programmable clock generator with spread  
spectrum capability. Spread spectrum modulates the output  
clock frequency over a small range, spreading the energy and  
reducing the energy peak. This is a powerful technique to reduce  
EMI in a variety of applications.  
■ Programmable Spread Spectrum with Nominal 31.5 kHz  
modulation Frequency  
■ Center Spread: ±0.25% to ±2.5%  
■ Down Spread: –0.5% to –5.0%  
It uses either an external reference clock or a crystal for an input.  
It also uses a PLL to generate a spread spectrum output clock  
that can be a different frequency than the input. Up to six output  
clocks are available and up to two of them can be REFCLKs  
(copies of the input clock, without spread).  
■ Input Frequency Range  
❐ External crystal: 8 to 30 MHz fundamental crystals  
❐ External reference: 8 to 166 MHz clock  
The CY25200 is highly configurable. Programmable variables  
include the input and output frequencies, spread percentage,  
center spread or down spread, and control pin functions. The  
oscillator pin capacitance can also be programmed to match the  
load capacitance requirement (CL) of the crystal, eliminating the  
need for external capacitors.  
■ Integrated Phase-Locked Loop (PLL)  
■ Programmable Crystal Load Capacitor Tuning Array  
■ Low Cycle-to-Cycle Jitter  
■ 3.3 V Operation with 2.5 V Output Clock Drive Option  
■ Spread Spectrum On and Off Function  
■ Power Down or Output Enable Function  
■ Output Frequency Select Option  
Available features include Output Enable, Power Down, Spread  
On/Off, Frequency Select, and the option to power some output  
clocks at 2.5 V.  
Cypress’ web-based CyberClocks Online software is used to  
configure the device. Programmability enables fast prototyping,  
which is particularly useful when doing EMC testing and  
determining the optimal spread settings.  
■ Field-Programmable  
■ Package: 16-pin TSSOP  
Logic Block Diagram  
SSCLK1  
SSCLK2  
7
Divider  
Bank 1  
8
Output  
Select  
Matrix  
9
SSCLK3  
SSCLK4  
XIN/CLKIN  
XOUT  
1
Q
OSC.  
12  
VCO  
16  
P
C
XOUT  
C
Divider  
Bank 2  
XIN  
PLL  
14  
15  
SSCLK5/REFOUT/CP2  
SSCLK6/REFOUT/CP3  
6
2
3
5
11  
4
10  
13  
AVSS VSS  
VDD  
AVDD  
VDDL VSSL  
CP0 CP1  
Cypress Semiconductor Corporation  
Document Number: 38-07633 Rev. *I  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised December 16, 2013  
1234567...17

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