CY25402

更新时间： 2024-09-30 06:51:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器
页数	文件大小	规格书
8页	259K
描述
Two PLL Programmable Clock Generator with Spread Spectrum

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中文翻译

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CY25402 数据手册

CY25402

CY25422

PRELIMINARY

Two PLL Programmable Clock Generator

with Spread Spectrum

Benefits

Features

• Two fully integrated phase-locked loops (PLLs)

• Input Frequency range:

• Multiple high-performance PLLs allow synthesis of

unrelated frequencies

• Nonvolatile programming for customized PLL frequencies,

spreadspectrumcharacteristics, drivestrength,crystalload

capacitance, and output frequencies

— External crystal: 8 to 48 MHz

— External reference: 8 to 166 MHz clock

• Wide operating output frequency range

— 3 to 166 MHz

• Two Spread Spectrum capable PLLs with Lexmark profile

for maximum for EMI reduction

• Spread Spectrum PLLs can be disabled or enabled

separately

• Programmable Spread Spectrum modulation frequency

range of 30 to 120 kHz with Lexmark profile

• PLLs can be programmed for system frequency margin

tests

• Center Spread: ±0.125% to ±2.5%

• Down Spread: –0.25% to –5%

• Meets critical timing requirements in complex system

designs

• Frequency select feature with option to select four different

frequencies

• Suitable for PC, consumer, and networking applications

• Ability to synthesize standard frequencies with ease

• Low-jitter, high-accuracy outputs

• Up to three clock outputs

• Application compatibility in standard and low-power

systems

• Programmable output drive strength

• Glitch-free outputs while frequency switching

• Four independent output voltages: 3.3V, 3.0V, 2.5V, and

1.8V

• 8-pin SOIC package

• Commercial and Industrial temperature range

Block Diagram

XIN

OSC

XOUT

Output

CLK1

Dividers

and

Drive

Strength

Control

PLL1

MUX

and

Control

Logic

CLK2

CLK3

(SS)

FS0

FS1

PLL2

(SS)

SSON

PD#/OE

Cypress Semiconductor Corporation

Document #: 001-12565 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 02, 2007

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