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CY25200_09 PDF预览

CY25200_09

更新时间: 2024-09-30 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器
页数 文件大小 规格书
11页 369K
描述
Programmable Spread Spectrum Clock Generator for EMI Reduction

CY25200_09 数据手册

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CY25200  
Programmable Spread Spectrum  
Clock Generator for EMI Reduction  
Features  
Benefits  
Wide operating output (SSCLK) frequency range  
3–200 MHz  
Suitable for most PC peripherals, networking, and consumer  
applications.  
Provides wide range of spread percentages for maximum EMI  
reduction to meet regulatory agency Electro Magnetic  
Compliance (EMC) requirements. Reduces development and  
manufacturing costs and time to market.  
Programmable spread spectrum with nominal 31.5 kHz  
modulation frequency  
Center spread: ±0.25% to ±2.5%  
Down spread: –0.5% to –5.0%  
Eliminates the need for expensive and difficult to use higher  
order crystals.  
Input frequency range  
External crystal: 8–30 MHz fundamental crystals  
External reference: 8–166 MHz clock  
Internal PLL generates up to 200 MHz outputs; also generates  
custom frequencies from an external crystal or a driven source.  
Integrated phase-locked loop (PLL)  
Programmable crystal load capacitor tuning array  
Low cycle-to-cycle jitter  
Enables fine tuning of output clock frequency by adjusting  
CLoad of the crystal. Eliminates the need for external CLoad  
capacitors.  
Application compatibility in standard and low power systems.  
3.3V operation with 2.5V output clock drive option  
Spread spectrum On and Off function  
Power down or Output Enable function  
Output frequency select option  
Provides ability to enable or disable spread spectrum with an  
external pin.  
Enables low power state or output clocks to High-Z state.  
Enables quick generation of sample prototype quantities.  
Field-programmable  
Package: 16 pin TSSOP  
Logic Block Diagram  
SSCLK1  
7
Divider  
Bank 1  
8
SSCLK2  
Output  
Select  
Matrix  
9
SSCLK3  
SSCLK4  
XIN/CLKIN  
XOUT  
1
Q
Φ
OSC.  
12  
VCO  
16  
P
C
XOUT  
C
Divider  
Bank 2  
XIN  
PLL  
14  
15  
SSCLK5/REFOUT/CP2  
SSCLK6/REFOUT/CP3  
6
2
3
5
11  
4 10  
CP0 CP1  
13  
AVSS VSS  
VDD  
AVDD  
VDDL VSSL  
Cypress Semiconductor Corporation  
Document #: 38-07633 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised May 22, 2008  
[+] Feedback  

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