CY2305SC-1

更新时间： 2024-01-20 04:17:34

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		动态存储器 PC
页数	文件大小	规格书
10页	134K
描述
CY2305 and CY2309 as PCI and SDRAM Buffers

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CY2305SC-1 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25	针数：	8
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	Factory Lead Time：	1 week
风险等级：	8.74	系列：	2305
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0	长度：	4.889 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	湿度敏感等级：	3
功能数量：	1	反相输出次数：
端子数量：	8	实输出次数：	8
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	220	电源：	3.3 V
传播延迟（tpd）：	8.7 ns	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.25 ns	座面最大高度：	1.727 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.8985 mm	最小 fmax：	133.33 MHz

CY2305SC-1 数据手册

CY2305 and CY2309 as PCI and SDRAM Buffers

buffer uses a input/output pad on CLKOUT so that the feed-

back signal can be sensed directly from the output itself.

Introduction to Cypress Zero Delay Buffers

What is a Zero Delay Buffer?

Drive Capability

A zero delay buffer is a device that can fan out 1 clock signal

The CY2305 and CY2309 have high drive outputs designed

to meet the JEDEC SDRAM specifications of 30 pF capaci-

tance on each DIMM clock input.

into multiple clock signals with zero delay and very low skew

between the outputs. This device is well suited as a buffer for

PCI or SDRAM due to its zero input to output delay and very

low output to output skew.

Since the typical CMOS input is 7 pF and the CY2305/09 are

designed to drive up to 30 pF; this means that up to 4 CMOS

inputs can be driven from a single output of a CY2305/09.

However the output loading on the CY2305/09 must be equal

on all outputs to maintain zero delay from the input.

A simplified diagram of the CY2308 zero delay buffer is shown

in Figure 1. The CY2308 is built using a PLL that uses a ref-

erence input and a feedback input. The feedback loop is

closed by driving the feedback input (FBK) from one of the

outputs. The phase detector in the PLL adjusts the output

frequency of the VCO so that the two inputs have no phase

difference. Since an output is one of the inputs to the PLL,

zero phase difference is maintained from REF to the output

driving FBK. Now if all outputs are uniformly loaded, zero

phase difference will be maintained from REF to all outputs.

This is a simple zero delay buffer. Introducing additional de-

vices (e.g., dividers) between the output and FBK can give

rise to some innovative applications for the PLL, and for fur-

ther information on these refer to the Cypress Application

Note “CY2308 Zero Delay Buffer”. Since many buffering ap-

plications require only a simple closure of the feedback loop,

Cypress has designed zero delay buffers with Internal Feed-

back Loops: the CY2305 and CY2309.

Power Down

The CY2305 and CY2309 have a unique power-down mode:

if the input reference is stopped, the part automatically enters

a shutdown state, shutting down the PLL and three-stating the

outputs. When the part is in shutdown mode it draws less than

50 µA, and can come out of shutdown mode with the PLL

locked in less than 1 ms. This power down mode can also be

entered by three-stating the input reference driver and allow-

ing the internal pull-down to pull the input LOW (the input

does not have to go LOW, it only has to stop).

5 Volt to 3.3 Volt Level Shifting

The CY2305 and CY2309 can act as a 5-volt to 3.3-volt level

shifter. The reference input pad is 5-volt signal-compatible.

Since many system components still operate at 5 volts, this

feature provides the capability to generate multiple 3.3-volt

clocks from a single 5-volt reference clock. This 5-volt sig-

nal-compatibility is only available on the reference pad; the

other input pads on the CY2309 are not 5-volt compatible.

What are the CY2305 and CY2309?

Cypress has designed zero delay buffers especially suited for

use with PCI or SDRAM buffering. The CY2305 and CY2309

have been designed with the feedback path integrated for

simpler system design. A simplified block diagram of the

CY2309 zero delay buffer is shown Figure 2. This zero delay

Phase

Detector

Loop

Filter

PLL

Phase

Detector

Loop

Filter

PLL

FBK

CLKOUT

VCO

REF

MUX

CLKA1

CLKA2

CLKA3

CLKA4

CLKA1

CLKA2

CLKA3

CLKA4

Select Input

Decoding

Select Input

Decoding

CLKB1

CLKB2

CLKB3

CLKB4

CLKB1

CLKB2

CLKB3

CLKB4

Figure 1. Simplified Block Diagram of CY2308

Figure 2. Simplified Block Diagram of CY2309

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

March 25, 1997 – Revised July 29, 1997

12 3 4 5 6 7...10

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CY2305SC-1 替代型号

型号	品牌	替代类型	描述	数据表
CY2305SC-1H	CYPRESS	完全替代	LOW-COST 3.3V ZERO DELAY BUFFER
CY2305SXI-1HT	CYPRESS	类似代替	Low-Cost 3.3V Zero Delay Buffer
CY2305SXC-1	CYPRESS	类似代替	Low-Cost 3.3V Zero Delay Buffer

与CY2305SC-1相关器件

型号	品牌	获取价格	描述	数据表
CY2305SC-1H	CYPRESS	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
CY2305SC-1HT	CYPRESS	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
CY2305SC-1T	CYPRESS	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
CY2305SI-1	CYPRESS	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
CY2305SI-1H	CYPRESS	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
CY2305SI-1HT	CYPRESS	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
CY2305SI-1T	CYPRESS	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
CY2305SXC-1	CYPRESS	获取价格	Low-Cost 3.3V Zero Delay Buffer
CY2305SXC-1	INFINEON	获取价格	3.3V Zero Delay Buffer
CY2305SXC-1H	CYPRESS	获取价格	Low-Cost 3.3V Zero Delay Buffer

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