CY2305SZC-1H

更新时间： 2024-11-20 03:30:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
14页	210K
描述
Low-Cost 3.3V Zero Delay Buffer

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CY2305SZC-1H 数据手册

CY2305

CY2309

Low-Cost 3.3V Zero Delay Buffer

CY2309. It accepts one reference input, and drives out five

low-skew clocks. The -1H versions of each device operate at

up to 100-/133-MHz frequencies, and have higher drive than

the -1 devices. All parts have on-chip PLLs which lock to an

input clock on the REF pin. The PLL feedback is on-chip and

is obtained from the CLKOUT pad.

The CY2309 has two banks of four outputs each, which can

be controlled by the Select inputs as shown in the “Select Input

Decoding” table on page 2. If all output clocks are not required,

BankB can be three-stated. The select inputs also allow the

input clock to be directly applied to the outputs for chip and

system testing purposes.

The CY2305 and CY2309 PLLs enter a power-down mode

when there are no rising edges on the REF input. In this state,

the outputs are three-stated and the PLL is turned off, resulting

in less than 12.0 µA of current draw for commercial temper-

ature devices and 25.0 µA for industrial temperature parts. The

CY2309 PLL shuts down in one additional case as shown in

the table below.

Multiple CY2305 and CY2309 devices can accept the same

input clock and distribute it. In this case, the skew between the

outputs of two devices is guaranteed to be less than 700 ps.

Features

• 10-MHz to 100-/133-MHz operating range, compatible

with CPU and PCI bus frequencies

• Zero input-output propagation delay

• 60 ps typical cycle-to-cycle jitter (high drive)

• Multiple low-skew outputs

— 85 ps typical output-to-output skew

— One input drives five outputs (CY2305)

— One input drives nine outputs, grouped as 4 + 4 + 1

(CY2309)

• Compatible with Pentium^-based systems

• Test Mode to bypass phase-locked loop (PLL) (CY2309

only [see “Select Input Decoding” on page 2])

• Available in space-saving 16-pin 150-mil SOIC or

4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil

SOIC package (CY2305)

• 3.3V operation

• Industrial temperature available

The CY2305/CY2309 is available in two/three different config-

urations, as shown in the ordering information (page 10). The

CY2305-1/CY2309-1 is the base part. The CY2305-1H/

CY2309-1H is the high-drive version of the -1, and its rise and

fall times are much faster than the -1s.

Functional Description

The CY2309 is a low-cost 3.3V zero delay buffer designed to

distribute high-speed clocks and is available in a 16-pin SOIC

or TSSOP package. The CY2305 is an 8-pin version of the

Block Diagram

Pin Configuration

SOIC/TSSOP

Top View

CLKOUT

PLL

MUX

REF

CLKA1

CLKOUT

REF

CLKA1

CLKA2

CLKA4

CLKA3

V_DD

CLKA2

V_DD

GND

CLKB1

CLKA3

CLKA4

CLKB4

CLKB3

CLKB2

CLKB1

CLKB2

CLKB3

CLKB4

SOIC

Top View

Select Input

Decoding

CLKOUT

CLK4

REF

CLK2

CLK1

CLK3

GND

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07140 Rev. *G

Revised August 4, 2005

12 3 4 5 6 7...14

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与CY2305SZC-1H相关器件

型号	品牌	获取价格	描述	数据表
CY2305SZC-1HT	CYPRESS	获取价格	Low-Cost 3.3V Zero Delay Buffer
CY2305SZC-1T	CYPRESS	获取价格	Low-Cost 3.3V Zero Delay Buffer
CY2305SZI-1	CYPRESS	获取价格	Low-Cost 3.3V Zero Delay Buffer
CY2305SZI-1H	CYPRESS	获取价格	Low-Cost 3.3V Zero Delay Buffer
CY2305SZI-1HT	CYPRESS	获取价格	Low-Cost 3.3V Zero Delay Buffer
CY2305SZI-1T	CYPRESS	获取价格	Low-Cost 3.3V Zero Delay Buffer
CY2305SZXC-1HT	CYPRESS	获取价格	PLL Based Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.150
CY2305SZZC-1T	CYPRESS	获取价格	PLL Based Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.150
CY2305ZC-1	CYPRESS	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
CY2305ZC-1T	CYPRESS	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER

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