Datasheet > CY2305ESXC-1HT

CY2305ESXC-1HT

更新时间： 2024-11-20 19:54:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
17页	383K
描述
Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY2305ESXC-1HT 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	8
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	风险等级：	5.57
系列：	2305	输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.889 mm	逻辑集成电路类型：	CLOCK DRIVER
湿度敏感等级：	1	功能数量：	1
反相输出次数：		端子数量：	8
实输出次数：	4	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	传播延迟（tpd）：	8.7 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.25 ns
座面最大高度：	1.727 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	3.8989 mm	最小 fmax：	133.33 MHz
Base Number Matches：	1

CY2305ESXC-1HT 数据手册

CY2305

CY2309

Low-Cost 3.3V Zero Delay Buffer

Features

Functional Description

■ 10MHzto100-/133MHzoperatingrange,compatiblewithCPU

and PCI bus frequencies

The CY2309 is a low-cost 3.3V zero delay buffer designed to

distribute high-speed clocks and is available in a 16-pin SOIC or

TSSOP package. The CY2305 is an 8-pin version of the

CY2309. It accepts one reference input, and drives out five

low-skew clocks. The -1H versions of each device operate at up

to 100-/133 MHz frequencies, and have higher drive than the -1

devices. All parts have on-chip PLLs which lock to an input clock

on the REF pin. The PLL feedback is on-chip and is obtained

from the CLKOUT pad.

■ Zero input-output propagation delay

■ 60 ps typical cycle-to-cycle jitter (high drive)

■ Multiple low-skew outputs

❐ 85 ps typical output-to-output skew

❐ One input drives five outputs (CY2305)

❐ One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309)

The CY2309 has two banks of four outputs each, which can be

controlled by the Select inputs as shown in the “Select Input

Decoding” table on page 3. If all output clocks are not required,

BankB can be three-stated. The select inputs also allow the input

clock to be directly applied to the outputs for chip and system

testing purposes.

■ Compatible with Pentium-based systems

■ Test Mode to bypass phase-locked loop (PLL) (CY2309 only

[see “Select Input Decoding” on page 3])

■ Available in space-saving 16-pin 150-mil SOIC or 4.4-mm

TSSOPpackages(CY2309), and8-pin, 150-milSOICpackage

(CY2305)

The CY2305 and CY2309 PLLs enter a power down mode when

there are no rising edges on the REF input. In this state, the

outputs are three-stated and the PLL is turned off, resulting in

less than 12.0 μA of current draw for commercial temperature

devices and 25.0 μA for industrial temperature parts. The

CY2309 PLL shuts down in one additional case as shown in the

table below.

■ 3.3V operation

■ Industrial temperature available

Multiple CY2305 and CY2309 devices can accept the same input

clock and distribute it. In this case, the skew between the outputs

of two devices is guaranteed to be less than 700 ps.

The CY2305/CY2309 is available in two/three different configu-

rations, as shown in the ordering information (page 12). The

CY2305-1/CY2309-1 is the base part. The CY2305-1H/

CY2309-1H is the high-drive version of the -1, and its rise and

fall times are much faster than the -1s.

Logic Block Diagram

CLKOUT

MUX

PLL

REF

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Select Input

Decoding

Cypress Semiconductor Corporation

Document #: 38-07140 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 23, 2008

[+] Feedback

12 3 4 5 6 7...17

中文翻译

下载PDF

与CY2305ESXC-1HT相关器件

型号	品牌	获取价格	描述	数据表
CY2305ESXC-1T	CYPRESS	获取价格	Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH
CY2305ESXI-1	CYPRESS	获取价格	PLL Based Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8,
CY2305ESXI-1H	CYPRESS	获取价格	PLL Based Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8,
CY2305ESXI-1HT	CYPRESS	获取价格	PLL Based Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8,
CY2305ESXI-1T	CYPRESS	获取价格	PLL Based Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8,
CY2305SC-1	CYPRESS	获取价格	CY2305 and CY2309 as PCI and SDRAM Buffers
CY2305SC-1H	CYPRESS	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
CY2305SC-1HT	CYPRESS	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
CY2305SC-1T	CYPRESS	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
CY2305SI-1	CYPRESS	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER

与CY2305ESXC-1HT相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

24
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

16
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

48
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

46

产品中心

服务支持

精选活动

关于我们

帮助中心

CY2305ESXC-1HT

CY2305ESXC-1HT 技术参数

CY2305ESXC-1HT 数据手册

与CY2305ESXC-1HT相关器件

与CY2305ESXC-1HT相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY2305ESXC-1HT

CY2305ESXC-1HT 技术参数

CY2305ESXC-1HT 数据手册

与CY2305ESXC-1HT相关器件

与CY2305ESXC-1HT相关文章

您还可以找

您在本页遇到什么问题？