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CY22U1LCXLGXI-YYT PDF预览

CY22U1LCXLGXI-YYT

更新时间: 2024-11-30 05:45:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟外围集成电路晶体
页数 文件大小 规格书
11页 321K
描述
Clock Generator, 200MHz, CMOS, 1.70 X 1.70 MM, 0.60 MM HEIGHT, LEAD FREE, QFN-8

CY22U1LCXLGXI-YYT 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:QFN包装说明:VQCCN,
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.21JESD-30 代码:S-XQCC-N8
JESD-609代码:e4长度:1.7 mm
湿度敏感等级:3端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:200 MHz封装主体材料:UNSPECIFIED
封装代码:VQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, VERY THIN PROFILE峰值回流温度(摄氏度):260
主时钟/晶体标称频率:166 MHz认证状态:Not Qualified
座面最大高度:0.8 mm最大供电电压:2 V
最小供电电压:1.6 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:NO LEAD端子节距:0.4 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:1.7 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

CY22U1LCXLGXI-YYT 数据手册

 浏览型号CY22U1LCXLGXI-YYT的Datasheet PDF文件第2页浏览型号CY22U1LCXLGXI-YYT的Datasheet PDF文件第3页浏览型号CY22U1LCXLGXI-YYT的Datasheet PDF文件第4页浏览型号CY22U1LCXLGXI-YYT的Datasheet PDF文件第5页浏览型号CY22U1LCXLGXI-YYT的Datasheet PDF文件第6页浏览型号CY22U1LCXLGXI-YYT的Datasheet PDF文件第7页 
PRELIMINARY  
UniClock CY22U1  
Single Output, Low Power Programmable  
Clock Generator  
Features  
Benefits  
Small Footprint, 8-Pin QFN 1.7 x 1.7 x 0.6 mm3 Package  
Services digital televisions and displays, set top boxes,  
multifunction printers, and a variety of consumer electronics  
applications.  
Low Power and Low Jitter Operation  
Multiple Operating Voltages:  
CY22U1S: 2.5V, 3.0V, or 3.3V  
CY22U1L: 1.8V  
Saves PCB space due to small form factor.  
Enables quick turnaround and flexibility and adaptability to  
design changes through programmability.  
Programmable Single Output Clock Generator Frequency  
Range:  
1 to 200 MHz  
Enables synthesis of highly accurate and stable output clock  
frequencies with zero or low PPM error.  
Enables fine tuning of output clock frequency by adjusting the  
crystal load CLoad using programmable internal capacitors.  
Crystal or External Reference Clock Input Frequency Range:  
Fundamental Tuned Crystal: 8 to 48 MHz  
External Reference Clock: 1 to 166 MHz  
Lowers clock solution cost by pairing a high frequency PLL  
programmability with a low cost, low frequency crystal.  
Programmable Capacitor Tuning Array  
Programmable PD# or OE Control Pin  
Enables low power during the power down or output disable  
function.  
Programmable Asynchronous or Synchronous OE and PD#  
Modes  
Provides flexibility for system applications through selectable  
asynchronous or synchronous output enable and disable.  
Logic Block Diagram  
Cypress Semiconductor Corporation  
Document Number: 001-50320 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 10, 2009  
[+] Feedback  

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