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CY2277APAC-12 PDF预览

CY2277APAC-12

更新时间： 2024-11-18 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动器电脑PC时钟
页数 文件大小 规格书
19页 209K
描述
Processor Specific Clock Generator, 83.3MHz, CMOS, PDSO48, TSSOP-48

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中文翻译

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CY2277APAC-12 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP-48
针数：48Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.85JESD-30 代码：R-PDSO-G48
JESD-609代码：e0长度：12.5 mm
端子数量：48最高工作温度：70 °C
最低工作温度：最大输出时钟频率：83.3 MHz
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源：2.5/3.3,3.3 V
主时钟/晶体标称频率：14.318 MHz认证状态：Not Qualified
座面最大高度：1.1 mm子类别：Clock Generators
最大压摆率：250 mA最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL宽度：6.1 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

CY2277APAC-12 数据手册

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7A  
CY2277A  
Pentium®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/  
Mobile PCs with Intel® 82430TX and 2 DIMMs or 3 SO-DIMMs  
The CY2277A has power-down, CPU stop and PCI stop pins  
for power management control. The CPU stop and PCI stop  
are controlled by the MODE pin. They are multiplexed with  
Features  
• Mixed 2.5V and 3.3V operation  
• Complete clock solution to meet requirements of Pen-  
SDRAM clock outputs, and are selected when the MODE pin  
is driven LOW. Additionally, these inputs are synchronized  
on-chip, enabling glitch-free transitions. When the  
CPU_STOP input is asserted, the CPU outputs are driven  
LOW. When the PCI_STOP input is asserted, the PCI outputs  
(except the free-running PCI clock) are driven LOW. Finally,  
when the PWR_DWN pin is asserted, the reference oscillator  
and PLLs are shut down, and all outputs are driven LOW.  
tium®, Pentium® II, 6x86, or K6 motherboards  
— Four CPU clocks at 2.5V or 3.3V  
— Up to eight 3.3V SDRAM clocks  
— Seven 3.3V synchronous PCI clocks, one free  
running  
— Two 3.3V USB/IO clocks at 48 or 24 MHz, selectable  
by serial interface  
— One 2.5V IOAPIC clock at 14.318 MHz  
— Two 3.3V Ref. clocks at 14.318 MHz  
• Factory-EPROM programmable CPU, PCI, and USB/IO  
clock frequencies for custom configuration  
The CY2277A outputs are designed for low EMI emission.  
Controlled rise and fall times, unique output driver circuits and  
factory-EPROM programmable output drive and slew-rate en-  
able optimal configurations for EMI control.  
• Factory-EPROM programmable output drive and slew  
rate for EMI customization  
CY2277A Selector Guide  
-12/  
• MODE Enable pin for CPU_STOP and PCI_STOP  
• SMBus serial configuration interface  
• Available in space-saving 48-pin SSOP and TSSOP  
packages.  
-12M/  
Clock Outputs  
CPU (60, 66.6 MHz)  
CPU (33.3, 66.6 MHz)  
-1/-1M  
-3  
--  
4
-7M  
4
-12I  
4
--  
--  
4
--  
--  
Functional Description  
CPU (SMBus select-  
able)  
--  
--  
--  
The CY2277A is a Clock Synthesizer/Driver for Pentium, Pen-  
tium II, 6X86, and K6 portable PCs designed with the Intel®  
82430TX or similar chipsets. There are three available options  
as shown in the selector guide  
PCI (CPU/2)  
7[1]  
6/8  
2
7[1]  
6/8  
2
7[1]  
6/8  
2
7[1]  
6/8  
2
SDRAM  
The CY2277A outputs four CPU clocks at 2.5V or 3.3V with up  
to nine selectable frequencies. There are up to eight 3.3V  
SDRAM clocks and seven PCI clocks, running at one half the  
CPU clock frequency. One of the PCI clocks is free-running.  
Additionally, the part outputs two 3.3V USB/IO clocks at 48  
MHz or 24 MHz, one 2.5V IOAPIC clock at 14.318 MHz, and  
two 3.3V reference clocks at 14.318 MHz. The CPU, PCI,  
USB, and IO clock frequencies are factory-EPROM program-  
mable for easy customization with fast turnaround times.  
USB/IO (48 or 24 MHz)  
IOAPIC (14.318 MHz)  
Ref (14.318 MHz)  
CPU-PCI delay  
1
1
1
1
2
2
2
2
1–6 ns 1–6 ns <1 ns 1–4 ns  
Note:  
1. One free-running PCI clock.  
Pin Configuration  
SSOP  
Logic Block Diagram  
IOAPIC (14.318 MHz)  
Top View  
V
DDQ2  
REF1  
REF0  
AV  
1
2
3
4
48  
47  
46  
45  
44  
43  
42  
41  
DD  
REF [0–1]  
(14.318)  
PWR_SEL  
XTALIN  
14.318  
MHz  
OSC.  
V
V
SS  
DDQ2  
XTALIN  
XTALOUT  
MODE  
XTALOUT  
IOAPIC  
PWR_DWN  
STOP  
CPU  
PLL  
CPUCLK[0–3]  
5
6
LOGIC  
V
SS  
V
CPUCLK0  
CPUCLK1  
7
8
9
10  
11  
DDQ3  
V
DDCPU  
PCICLK_F  
PCICLK0  
SDRAM[0–5]  
V
SEL  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
EPROM  
DDCPU  
V
SS  
CPUCLK2  
CPUCLK3  
PCICLK1  
PCICLK2  
MODE  
SDRAM6/CPU_STOP  
12  
13  
V
SYS  
PLL  
SS  
PCICLK3  
PCICLK4  
SDRAM0  
SDRAM1  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
SDRAM7/PCI_STOP  
V
DDQ3  
V
DDQ3  
/2  
PCICLK5  
SDRAM2  
SDRAM3  
V
SS  
Delay  
SEL  
V
PWR_DWN  
STOP  
LOGIC  
SS  
PCI[0–5]  
SDATA  
SCLK  
30  
29  
28  
27  
26  
25  
SDRAM4  
SDRAM5  
PCICLK_F  
SERIAL  
SCLK  
V
V
DDQ3  
DDQ3  
Divide and  
Mux Logic  
INTERFACE  
CONTROL  
LOGIC  
USBCLK/IOCLK[0:1]  
USBCLK/IOCLK  
USBCLK/IOCLK  
SDRAM6/CPU_STOP  
SDRAM7/PCI_STOP  
SDATA  
V
AV  
DD  
SS  
Cypress Semiconductor Corporation  
Document #: 38-07332 Rev. *A  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised December 7, 2002  
1234567...19

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