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CY143

更新时间: 2024-01-08 04:33:17
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
14页 195K
描述
2K x 16 Dual-Port Static RAM(193.25 k)

CY143 数据手册

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CY7C133  
CY7C143  
2K x 16 Dual-Port Static RAM  
Features  
Functional Description  
• True dual-ported memory cells which allow  
The CY7C133 and CY7C143 are high-speed CMOS 2K by 16  
dual-port static RAMs. Two ports are provided permitting inde-  
pendent access to any location in memory. The CY7C133 can  
be utilized as either a stand-alone 16-bit dual-port static RAM  
or as a master dual-port RAM in conjunction with the CY7C143  
slave dual-port device in systems requiring 32-bit or greater  
word widths. It is the solution to applications requiring shared  
or buffered data, such as cache memory for DSP, bit-slice, or  
multiprocessor designs.  
simultaneous reads of the same memory location  
• 2K x 16 organization  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 25/35/55 ns  
• Low operating power: I = 150 mA (typ.)  
CC  
• Fully asynchronous operation  
• Master CY7C133 expands data bus width to 32 bits or  
more using slave CY7C143  
• BUSY input flag on CY7C133; BUSY output flag on  
CY7C143  
• Available in 68-pin PLCC  
Each port has independent control pins; Chip Enable (CE),  
Write Enable (R/W , R/W ), and Output Enable (OE). BUSY  
UB  
LB  
signals that the port is trying to access the same location cur-  
rently being accessed by the other port. An automatic pow-  
er-down feature is controlled independently on each port by  
the Chip Enable (CE) pin.  
• Pin-compatible and functionally equivalent to IDT7133  
and IDT7143  
The CY7C133 and CY7C143 are available in 68-pin PLCC.  
Logic Block Diagram  
CE  
R
CE  
L
R/W  
LUB  
R/W  
RUB  
R/W  
RLB  
R/W  
LLB  
OE  
R
OE  
L
I/O – I/O  
I/O – I/O  
8R  
8L  
15L  
15R  
I/O  
CONTROL  
I/O  
CONTROL  
I/O – I/O  
I/O – I/O  
0R  
0L  
7L  
7R  
[
]
1
[1]  
BUSY  
BUSY  
R
L
A
A
10L  
10R  
0R  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
MEMORY  
ARRAY  
A
0L  
A
ARBITRATION  
LOGIC  
CE  
OE  
CE  
L
L
R
OE  
R
(CY7C133ONLY)  
R/W  
R/W  
RUB  
RLB  
LUB  
R/W  
C133-1  
R/W  
LLB  
Note:  
1. CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
October 14, 1999  

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