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CXD2586R PDF预览

CXD2586R

更新时间: 2024-01-16 10:52:53
品牌 Logo 应用领域
索尼 - SONY 消费电路商用集成电路数字信号处理器
页数 文件大小 规格书
127页 1684K
描述
CD Digital Signal Processor with Built-in Digital Servo and DAC

CXD2586R 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP, QFP144,.87SQ,20针数:144
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:S-PQFP-G144
长度:20 mm功能数量:1
端子数量:144最高工作温度:75 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP144,.87SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
电源:5 V认证状态:Not Qualified
座面最大高度:1.7 mm子类别:Other Consumer ICs
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL EXTENDED端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:20 mmBase Number Matches:1

CXD2586R 数据手册

 浏览型号CXD2586R的Datasheet PDF文件第1页浏览型号CXD2586R的Datasheet PDF文件第2页浏览型号CXD2586R的Datasheet PDF文件第3页浏览型号CXD2586R的Datasheet PDF文件第5页浏览型号CXD2586R的Datasheet PDF文件第6页浏览型号CXD2586R的Datasheet PDF文件第7页 
CXD2586R/-1  
Pin Description  
Pin  
Symbol  
No.  
I/O  
Description  
SE  
I
I
1
2
Sled error signal input.  
Focus error signal input.  
Center voltage input.  
FE  
VC  
I
3
VPCO1  
VPCO2  
VCTL  
FILO  
O
O
I
1, Z, 0  
1, Z, 0  
4
Wide-band EFM PLL VCO2 charge pump output.  
Wide-band EFM PLL VCO2 charge pump output.  
Wide-band EFM PLL VCO2 control voltage input.  
Master PLL filter output (slave = digital PLL).  
Master PLL filter input.  
5
6
O
I
Analog  
1, Z, 0  
7
FILI  
8
PCO  
O
I
9
Master PLL charge pump output.  
Master VCO control voltage input.  
Analog GND.  
CLTV  
AVSS1  
RFAC  
BIAS  
ASYI  
ASYO  
AVDD1  
DVDD1  
ASYE  
PSSL  
WDCK  
LRCK  
LRCKI  
10  
11  
12  
13  
14  
15  
16  
18  
19  
20  
21  
22  
23  
I
I
EFM signal input.  
Asymmetry circuit constant current input.  
Asymmetry comparator voltage input.  
EFM full-swing output (low = VSS, high = VDD).  
Analog power supply.  
I
O
1, 0  
Digital power supply.  
I
I
Asymmetry circuit on/off (low = off, high = on).  
Audio data output mode switching input (low = serial, high = parallel).  
D/A interface for 48-bit slot. Word clock f = 2Fs.  
D/A interface for 48-bit slot. LR clock f = Fs.  
O
O
I
1, 0  
1, 0  
LR clock input to DAC (48-bit slot).  
DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two's  
complement, MSB first) when PSSL = 0.  
DA16  
O
1, 0  
1, 0  
1, 0  
24  
PCMDI  
DA15  
BCKI  
I
O
I
25  
26  
27  
Audio data input to DAC (48-bit slot).  
DA15 output when PSSL = 1, 48-bit slot bit clock output when PSSL = 0.  
Bit clock input to DAC (48-bit slot).  
DA14 output when PSSL = 1, 64-bit slot serial data output (two's  
complement, LSB first) when PSSL = 0.  
DA14  
O
28  
DA13  
DA12  
DA11  
DA10  
DA09  
DA08  
DA07  
O
O
O
O
O
O
O
1, 0  
1, 0  
1, 0  
1, 0  
1, 0  
1, 0  
1, 0  
29  
31  
32  
33  
34  
35  
36  
DA13 output when PSSL = 1, 64-bit slot bit clock output when PSSL = 0.  
DA12 output when PSSL = 1, 64-bit slot LR clock output when PSSL = 0.  
DA11 output when PSSL = 1, GTOP output when PSSL = 0.  
DA10 output when PSSL = 1, XUGF output when PSSL = 0.  
DA09 output when PSSL = 1, XPLCK output when PSSL = 0.  
DA08 output when PSSL = 1, GFS output when PSSL = 0.  
DA07 output when PSSL = 1, RFCK output when PSSL = 0.  
– 4 –  

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