CXD2586R-1

更新时间： 2024-01-02 10:24:10

品牌	Logo	应用领域
索尼 - SONY		消费电路商用集成电路数字信号处理器
页数	文件大小	规格书
127页	1684K
描述
CD Digital Signal Processor with Built-in Digital Servo and DAC

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技术参数
数据手册

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CXD2586R-1 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LFQFP, QFP144,.87SQ,20
针数：	144	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.88
Is Samacsys：	N	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-PQFP-G144	JESD-609代码：	e0
长度：	20 mm	功能数量：	1
端子数量：	144	最高工作温度：	75 °C
最低工作温度：	-20 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP144,.87SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.7 mm
子类别：	Other Consumer ICs	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL EXTENDED
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	20 mm
Base Number Matches：	1

CXD2586R-1 数据手册

CXD2586R/-1

CD Digital Signal Processor with Built-in Digital Servo and DAC

For the availability of this product, please contact the sales office.

Description

The CXD2586R/-1 is a digital signal processor LSI

for CD players. This LSI incorporates the digital

servo, digital filter and 1-bit DAC.

144 pin LQFP (Plastic)

Features

• All digital signal processing during playback is

performed with a single chip

• Highly integrated mounting possible due to a built-

in RAM

Digital Signal Processor Block

• Playback mode which supports CAV (Constant

Angular Velocity)

• Frame jitter free

Structure

• Half-speed to octuple-speed continuous playback

possible with a low external clock (only CXD2586R-1

supports up to octuple speed)

Silicon gate CMOS IC

Absolute Maximum Ratings

• Supply voltage

• Input voltage

• Allows relative rotational velocity readout

• Wide capture range playback mode

• Spindle rotational velocity following method

• Supports normal-speed, double-speed, quadruple-

speed, sextuple-speed and octuple-speed playback

(only CXD2586R-1)

VDD

–0.3 to +7.0

(V^SS– 0.3V to VDD +0.3V)

• Output voltage

–0.3 to +7.0 V

–40 to +125 °C

• Storage temperature Tstg

• Supply voltage difference VSS – AVSS –0.3 to +0.3

• Wide frame jitter margin (±28 frames) due to a

built-in 32K RAM

VDD – AVDD –0.3 to +0.3

• The bit clock, which strobes the EFM signal, is

generated by the digital PLL

Recommended Operating Conditions

• Supply voltage

• Operating temperature

• EFM data demodulation

• Enhanced EFM frame sync signal protection

• Refined super strategy-based powerful error correction

C1: double correction, C2: quadruple correction

• Octuple-speed (only CXD2586R-1), sextuple-speed,

quadruple-speed and double-speed playback (digital

signal processor and digital servo blocks)

• Noise reduction during track jumps

• Auto zero-cross mute

The VDD (min.) for the CXD2586R/-1 varies according

to the playback speed and built-in VCO selection. The

VDD (min.) is 4.5V when high-speed VCO and

quadruple-speed playback are selected (variable pitch

off). The VDD (min.) for the CXD2586R/-1 under

various conditions are as shown in the following table.

VDD (min.) [V]

Playback

• Subcode demodulation and Sub Q data error detection

• Digital spindle servo (with oversampling filter)

• 16-bit traverse counter

DAC

block

VCO1 high VCO1 normal

speed

• Asymmetry compensation circuit

• CPU interface on serial bus

× 8

4.75

—

• Error correction monitor signal, etc. output from a

new CPU interface

(only CXD2586R-1)

× 6

× 4

4.50

4.00

3.40

—

• Servo auto sequencer

• Fine search performs track jumps with high accuracy

• Digital audio interface outputs

• Digital level meter, peak meter

• Bilingual compatible

× 2

—

× 2

4.00

3.40

—

Digital Servo Block

• Microcomputer software-based flexible servo control

• Servo error signal, offset cancel function

• Servo loop, auto gain control function

• E:F balance, focus bias adjustment function

× 1

—

× 1

4.50

—: Dashes indicate that there is no assurance of the

processor operating. All values are for variable pitch off.

Digital Filters (DAC and LPF blocks)

• Low-pass filter for DAC

When the internal operation of the LSI is set to normal-

speed playback and the operating clock of the signal

processor is doubled, double-speed playback results.

• Digital de-emphasis

• Digital attenuation

When the internal operation of the LSI is set to double-

• 4fs oversampling filter

speed mode and the crystal oscillating frequency is

halved in low power consumption mode, normal-speed

playback results.

• Adopts secondary ∆∑ noise shaper

• LPF for DAC analog output

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E95Y01A65-ST

12 3 4 5 6 7...127

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