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CX02K336K PDF预览

CX02K336K

更新时间: 2024-11-06 21:21:59
品牌 Logo 应用领域
基美 - KEMET 电容器
页数 文件大小 规格书
86页 630K
描述
Tantalum Capacitor, Polarized, Tantalum (dry/solid), 25V, 10% +Tol, 10% -Tol, 33uF, Through Hole Mount, RADIAL LEADED

CX02K336K 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active包装说明:RADIAL LEADED
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8532.21.00.40风险等级:5.63
电容:33 µF电容器类型:TANTALUM CAPACITOR
介电材料:TANTALUM (DRY/SOLID)ESR:1200 m Ω
高度:15.49 mmJESD-609代码:e0
漏电流:0.0066 mA长度:8.89 mm
安装特点:THROUGH HOLE MOUNT负容差:10%
端子数量:2最高工作温度:125 °C
最低工作温度:-55 °C封装形状:DISK PACKAGE
封装形式:Radial包装方法:AMMO PACK
极性:POLARIZED正容差:10%
额定(直流)电压(URdc):25 V参考标准:MIL-PRF-49137
表面贴装:NODelta切线:0.06
端子面层:Tin/Lead (Sn/Pb)端子节距:6.35 mm
端子形状:WIREBase Number Matches:1

CX02K336K 数据手册

 浏览型号CX02K336K的Datasheet PDF文件第2页浏览型号CX02K336K的Datasheet PDF文件第3页浏览型号CX02K336K的Datasheet PDF文件第4页浏览型号CX02K336K的Datasheet PDF文件第5页浏览型号CX02K336K的Datasheet PDF文件第6页浏览型号CX02K336K的Datasheet PDF文件第7页 
ACEX 1K  
Programmable Logic Device Family  
®
May 2001, ver. 3.0  
Data Sheet  
 
Programmable logic devices (PLDs), providing low cost  
system-on-a-programmable-chip (SOPC) integration in a single  
device  
Features...  
Enhanced embedded array for implementing megafunctions  
such as efficient memory and specialized logic functions  
Dual-port capability with up to 16-bit width per embedded array  
block (EAB)  
Logic array for general logic functions  
 
 
High density  
10,000 to 100,000 typical gates (see Table 1)  
Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be  
used without reducing logic capacity)  
Cost-efficient programmable architecture for high-volume  
applications  
Cost-optimized process  
Low cost solution for high-performance communications  
applications  
 
System-level features  
MultiVoltTM I/ O pins can drive or be driven by 2.5-V, 3.3-V, or  
5.0-V devices  
Low power consumption  
Bidirectional I/ O performance (setup time [t ] and clock-to-  
SU  
output delay [t ]) up to 250 MHz  
CO  
Fully compliant with the peripheral component interconnect  
Special Interest Group (PCI SIG) PCI Local Bus Specification,  
Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz  
TM  
Table 1. ACEX 1K Device Features  
Feature  
EP1K10  
EP1K30  
EP1K50  
EP1K100  
Typical gates  
10,000  
56,000  
576  
30,000  
119,000  
1,728  
6
50,000  
199,000  
2,880  
10  
100,000  
257,000  
4,992  
12  
Maximum system gates  
Logic elements (LEs)  
EABs  
3
Total RAM bits  
12,288  
136  
24,576  
171  
40,960  
249  
49,152  
333  
Maximum user I/O pins  
Altera Corporation  
1
A-DS-ACEX-03.0  
 

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