Datasheet > 信号电路 > 锁相环或频率合成电路> CS2000-OTP

CS2000-OTP

更新时间： 2024-01-30 09:53:30

品牌	Logo	应用领域
凌云 - CIRRUS		时钟
页数	文件大小	规格书
30页	251K
描述
Fractional-N Clock Synthesizer & Clock Multiplier

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CS2000-OTP 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	TSSOP, TSSOP10,.19,20	Reach Compliance Code：	compliant
风险等级：	5.7	模拟集成电路 - 其他类型：	PHASE LOCKED LOOP
JESD-30 代码：	S-PDSO-G10	长度：	3 mm
功能数量：	1	端子数量：	10
最高工作温度：	105 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP10,.19,20	封装形状：	SQUARE
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
座面最大高度：	1.1 mm	最大供电电流 (Isup)：	18 mA
最大供电电压 (Vsup)：	3.5 V	最小供电电压 (Vsup)：	3.1 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	HYBRID	温度等级：	AUTOMOTIVE
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3 mm	Base Number Matches：	1

CS2000-OTP 数据手册

CS2000-OTP

4. ARCHITECTURE OVERVIEW

4.1

Delta-Sigma Fractional-N Frequency Synthesizer

The core of the CS2000 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolu-

tion for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to

quickly tune to a new frequency. In very simplistic terms, the Fractional-N Frequency Synthesizer multiplies

the Timing Reference Clock by the value of N to generate the PLL output clock. The desired output to input

clock ratio is the value of N that is applied to the delta-sigma modulator (see Figure 5).

The analog PLL based frequency synthesizer uses a low-jitter timing reference clock as a time and phase

reference for the internal voltage controlled oscillator (VCO). The phase comparator compares the fraction-

al-N divided clock with the original timing reference and generates a control signal. The control signal is fil-

tered by the internal loop filter to generate the VCO’s control voltage which sets its output frequency. The

delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio between the

reference clock and the VCO output (thus the duty cycle of the modulator sets the fractional value). This

allows the design to be optimized for very fast lock times for a wide range of output frequencies without the

need for external filter components. As with any Fractional-N Frequency Synthesizer the timing reference

clock should be stable and jitter-free.

Timing Reference

Clock

Phase

Comparator

Internal

Loop Filter

Voltage Controlled

Oscillator

PLL Output

Fractional-N

Divider

Delta-Sigma

Modulator

Figure 5. Delta-Sigma Fractional-N Frequency Synthesizer

4.2

Hybrid Analog-Digital Phase Locked Loop

The addition of the Digital PLL and Fractional-N Logic (shown in Figure 6) to the Fractional-N Frequency

Synthesizer creates the Hybrid Analog-Digital Phase Locked Loop with many advantages over classical an-

alog PLL techniques. These advantages include the ability to operate over extremely wide frequency ranges

without the need to change external loop filter components while maintaining impressive jitter reduction per-

formance. In the Hybrid architecture, the Digital PLL calculates the ratio of the PLL output clock to the fre-

quency reference and compares that to the desired ratio. The digital logic generates a value of N which is

then applied to the Fractional-N frequency synthesizer to generate the desired PLL output frequency. Notice

that the frequency and phase of the timing reference signal do not affect the output of the PLL since the

digital control loop will correct for the PLL output. A major advantage of the Digital PLL is the ease with which

the loop filter bandwidth can be altered. The PLL bandwidth is set to a wide-bandwidth mode to quickly

achieve lock and then reduced for optimal jitter rejection.

DS758F1

1...6 7 8910 11 12...30

中文翻译

下载PDF

与CS2000-OTP相关器件

型号	品牌	描述	获取价格	数据表
CS2000-OTP_09	CIRRUS	Fractional-N Clock Synthesizer & Clock Multiplier	获取价格
CS2000P-CZZ	CIRRUS	Fractional-N Clock Synthesizer & Clock Multiplier	获取价格
CS2000P-CZZR	CIRRUS	Fractional-N Clock Synthesizer & Clock Multiplier	获取价格
CS2000P-DZZ	CIRRUS	Phase Locked Loop, Hybrid, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10	获取价格
CS2000P-DZZR	CIRRUS	Phase Locked Loop, Hybrid, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10	获取价格
CS2001	ONSEMI	1.2 A Switching Regulator, and 5.0 V, 100 mA Linear Regulator with RESET	获取价格

与CS2000-OTP相关文章

深入解析CS8416引脚说明、参数、技术特点
2024-06-03

1
TPA3116D2功放芯片参数详解、引脚说明
2024-06-03

5
移位寄存器74HC165引脚说明、驱动程序示例解读
2024-06-03

5
深入解析AD9833：DDS频率合成器的卓越性能与广泛应用
2024-06-03

2

产品中心

服务支持

精选活动

关于我们

帮助中心

CS2000-OTP

CS2000-OTP 技术参数

CS2000-OTP 数据手册

与CS2000-OTP相关器件

与CS2000-OTP相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CS2000-OTP

CS2000-OTP 技术参数

CS2000-OTP 数据手册

与CS2000-OTP相关器件

与CS2000-OTP相关文章

您还可以找

您在本页遇到什么问题？